| ebe69fe11e48d322045d5949c83283927a0d790b |
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23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/test/MC/X86/x86_64-encoding.s
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| c6f7c99809cece8c85e180c1b95e6159d8ea9613 |
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14-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86_64-encoding.s
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| bae9f69d37a60aad0185cdf17434ec188c976e67 |
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14-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192565 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86_64-encoding.s
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| 15de63cfdedc9a449217c841f8e084387b2159c8 |
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10-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Allow non-AVX form of pmovmskb to take a GR64 operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192341 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86_64-encoding.s
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| a247e9d42b03851be8425631e2716d4ff9f37c47 |
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14-Sep-2013 |
Ben Langmuir <ben.langmuir@intel.com> |
Add the remaining Intel SHA instructions
Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit
xmm0 dependency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86_64-encoding.s
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| 1f1bd9a54d25d4e2c5da13c2cae7fa5e3d8acc9f |
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12-Sep-2013 |
Ben Langmuir <ben.langmuir@intel.com> |
Partial support for Intel SHA Extensions (sha1rnds4)
Add basic assembly/disassembly support for the first Intel SHA
instruction 'sha1rnds4'. Also includes feature flag, and test cases.
Support for the remaining instructions will follow in a separate patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86_64-encoding.s
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| c25e8d8cea7af83b5538ac0e521366d06c9720d9 |
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15-Apr-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Add encoding tests for flds/filds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129589 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86_64-encoding.s
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| 97755a063eb65705e928550b048ecb921c83545c |
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18-Feb-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Recognize leavel and leaveq aliases for leave.
Validate encoding of leave in 64bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125795 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86_64-encoding.s
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| 26f23100ac8165c510c00f7a37f1ab13bf66f141 |
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13-Feb-2011 |
Reid Kleckner <reid@kleckner.net> |
Add encodings and mnemonics for FXSAVE64 and FXRSTOR64.
These are just FXSAVE and FXRSTOR with REX.W prefixes. These versions use
64-bit pointer values instead of 32-bit pointer values in the memory map they
dump and restore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86_64-encoding.s
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| 3286db670c689104c0df4f98fbb4a66f6e4d2db5 |
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01-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
move X86 subdir up a level
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86_64-encoding.s
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