Cross Reference: /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4

History log of /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
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fc10dc9fdea6ad7d04dfcdb8fd2e2d59ea67f68b	22-Dec-2016	Rob Clark <robdclark@gmail.com>	freedreno/ir3: rework location of driver constants Rework how we lay out driver constants (driver-params, UBO/TFBO buffer addresses, immediates) for more flexibility. For a5xx+ we need to deal with the fact that gpu ptrs are 64b instead of 32b, which makes the fixed offset scheme not work so well. While we are dealing with that we might also make the layout more dynamic to account for varying # of UBOs, etc. Signed-off-by: Rob Clark <robdclark@gmail.com> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
bea8602e5b576eb98d8e4657f2b1287fb9f148a1	12-Dec-2016	Rob Clark <robdclark@gmail.com>	freedreno: fdN_gmem_restore_format() is not gen specific Refactor out into a common helper, since this is the same across generations when we need equiv z/s gmem restore format. Next patch needs this in a5xx, rather than creating yet another helper push this into core. Signed-off-by: Rob Clark <robdclark@gmail.com> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
fcba3046e1b90ecec6f5f4ad5397cd36e0c740ac	08-Nov-2016	Rob Clark <robdclark@gmail.com>	freedreno: update generated headers Pull in a5xx Signed-off-by: Rob Clark <robdclark@gmail.com> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
b8b800d18a75d8d919239a91be07ac0aee42fa0d	09-Nov-2016	Rob Clark <robdclark@gmail.com>	freedreno/a4xx: make _emit_const() static Signed-off-by: Rob Clark <robdclark@gmail.com> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
89f00f749fda4c1beca38f362c7f86bdc6e32785	15-Aug-2016	Ilia Mirkin <imirkin@alum.mit.edu>	a4xx: make sure to actually clamp depth as requested We were previously ... not clamping. I guess this meant that everything got clamped to 1/0, which was enough to pass the existing tests. Or perhaps the clamping would only happen to the rasterized depth value and not the frag shader's output depth value. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97231 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: mesa-stable@lists.freedesktop.org /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
9f0eb6952790bffe2670f26d399f15acec199cac	19-Jul-2016	Rob Clark <robdclark@gmail.com>	freedreno: drop needs_rb_fbd We need to emit RB_FRAME_BUFFER_DIMENSION once per batch.. tracking this in fd_context is wrong when the gmem code executes asynchronously from the flush_queue worker. But in fact we don't really need to track it at all. We cannot assume previous value at the beginning of the batch (because of other processes potentially using the GPU), so just drop the tracking and emit it in _tile_init(). Signed-off-by: Rob Clark <robdclark@gmail.com> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
e6bfe1c7734cfbf41a763797527db6cb49fa1566	19-Jul-2016	Rob Clark <robdclark@gmail.com>	freedreno: move needs_wfi into batch This is also used in gmem code, which executes from the "bottom half" (ie. from the flush_queue worker thread), so it cannot be in fd_context. Signed-off-by: Rob Clark <robdclark@gmail.com> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
7f8fd02dc7cad1ddcfb610db10ffbb41e3e34e7d	11-Jul-2016	Rob Clark <robdclark@gmail.com>	freedreno: re-order support for hw queries Push query state down to batch, and use the resource tracking to figure out which batch(es) need to be flushed to get the query result. This means we actually need to allocate the prsc up front, before we know the size. So we have to add a special way to allocate an un- backed resource, and then later allocate the backing storage. Signed-off-by: Rob Clark <robdclark@gmail.com> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
f02a64dbdd2ec147167ad60357bd46d8d964290a	27-Jun-2016	Rob Clark <robdclark@gmail.com>	freedreno: move more batch related tracking to fd_batch To flush batches out of order, the gmem code needs to not depend on state from fd_context (since that may apply to a more recent batch). So this all moves into batch. The one exception is the gmem/pipe/tile state itself. But this is only used from gmem code (and batches are flushed serially). The alternative would be having to re-calculate GMEM layout on every batch, even if the dimensions of the render targets are the same. Note: This opens up the possibility of pushing gmem/submit into a helper thread. Signed-off-by: Rob Clark <robdclark@gmail.com> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
9bbd239a4039522d7c1023ecb21764679447bb2d	20-May-2016	Rob Clark <robclark@freedesktop.org>	freedreno: introduce fd_batch Introduce the batch object, to track a batch/submit's worth of ringbuffers and other bookkeeping. In this first step, just move the ringbuffers into batch, since that is mostly uninteresting churn. For now there is just a single batch at a time. Note that one outcome of this change is that rb's are allocated/freed on each use. But the expectation is that the bo pool in libdrm_freedreno will save us the GEM bo alloc/free which was the initial reason to implement a rb pool in gallium. The purpose of the batch is to eventually facilitate out-of-order rendering, with batches associated to framebuffer state, and tracking the dependencies on other batches. Signed-off-by: Rob Clark <robdclark@gmail.com> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
88cc11e971e8e84c2704a86b325a08cbe8ffc354	20-May-2016	Rob Clark <robclark@freedesktop.org>	freedreno: switch emit_const_bo() to take prsc's We can push the unwrap of pipe_resource down. Signed-off-by: Rob Clark <robdclark@gmail.com> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
11f065240438728c36c777ff8fcedd3d32426c3c	01-Jun-2016	Rob Clark <robclark@freedesktop.org>	freedreno/a4xx: only update/emit bordercolor state when needed I noticed in stk that it was contributing to a lot of overhead. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
291ac872a445f3edebd668b27e910a79e1de5a00	03-May-2016	Rob Clark <robclark@freedesktop.org>	freedreno: move shader-stage dirty bits to global dirty flag This was always a bit overly complicated, and had some issues (like ctx->prog.dirty not getting reset at the end of the batch). It also required some special hacks to avoid resetting dirty state on binning pass. So just move it all into ctx->dirty (leaving some free bits for future shader stages), and make FD_DIRTY_PROG just be the union of all FD_SHADER_DIRTY_*. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
a48cccacf3c7d655bbca42b51193100b43eeff6e	03-May-2016	Rob Clark <robclark@freedesktop.org>	freedreno/a4xx: fix bogus offset for f32x24s8 stencil restore fixes: $piglit/bin/fbo-clear-formats GL_ARB_depth_buffer_float Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
173871dfb988c3e9fb74a8016d2b024619a5d918	11-Apr-2016	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: lower immeds to const Helps reduce register pressure and instruction counts for immediates that would otherwise require a mov into gpr. total instructions in shared programs: 4455332 -> 4369297 (-1.93%) total dwords in shared programs: 8807872 -> 8614432 (-2.20%) total full registers used in shared programs: 263062 -> 250846 (-4.64%) total half registers used in shader programs: 9845 -> 9845 (0.00%) total const registers used in shared programs: 1029735 -> 1466993 (42.46%) half full const instr dwords helped 0 10415 0 17861 5912 hurt 0 1157 21458 947 33 Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
adf795432f788b33822d3a94b704be4ca536c8f1	19-Apr-2016	Rob Clark <robclark@freedesktop.org>	freedreno/a4xx: better workaround for astc+srgb This seems like a hw bug, and maybe only applies to certain a4xx variants/revisions. But setting the SRGB bit in sampler view state (texconst0) causes invalid alpha for ASTC textures. Work around this setting up a second texture state and using that to sample alpha separately. This way, srgb->linear conversion happens in hw prior to interpolation. This fixes 546 dEQP tests: dEQP-GLES3.functional.texture.astcsrgb* Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
19118e6f4713fd90d1a0bb75cbb2c06f1043d378	22-Apr-2016	Rob Clark <robclark@freedesktop.org>	freedreno/a4xx: blend state no longer depends on fb state Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
e85bef8b128eef7ae549a95bac197601435da9cd	22-Apr-2016	Rob Clark <robclark@freedesktop.org>	freedreno/a4xx: fix encoding of blend color state Fixes a whole bunch of dEQP-GLES3.functional.fragment_ops.random.* (now they all pass) Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
fb523cb6ad3ffef22ab4b9cce9e53859c17c5739	16-Apr-2016	Marek Olšák <marek.olsak@amd.com>	gallium: merge PIPE_SWIZZLE_* and UTIL_FORMAT_SWIZZLE_* Use PIPE_SWIZZLE_* everywhere. Use X/Y/Z/W/0/1 instead of RED, GREEN, BLUE, ALPHA, ZERO, ONE. The new enum is called pipe_swizzle. Acked-by: Jose Fonseca <jfonseca@vmware.com> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
f68c6951b86ac38ebdb89bc6b5a6285433e684a6	05-Mar-2016	Rob Clark <robclark@freedesktop.org>	freedreno/a4xx: hw binning Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
2224ba597629b299e8601a137ead54ad5d93c489	05-Mar-2016	Rob Clark <robclark@freedesktop.org>	freedreno/a4xx: remove RB_RENDER_CONTROL patching Bitfields where shuffled around for the better on a4xx, so we don't need any patching on this one. It appears to be something we set entirely in the gmem code so no conflict between tiling and render state like we had in a3xx. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
5b955f09f72b2217576ea8980a3d8fd3ba63854a	07-Mar-2016	Rob Clark <robclark@freedesktop.org>	freedreno/a4xx: constify the shader variants Most of the driver just needs read-only access, so constify.. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
c3f2f8cbe47a51087dcc82826bd939786c812366	01-Mar-2016	Rob Clark <robclark@freedesktop.org>	freedreno/ir3: pass ctx to constant-emit code Rather than fishing it out of the shader. This removes the other big user of shader->pctx. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
8529e210ecb2aa362f51399f8632c6d4429401cf	10-Feb-2016	Rob Clark <robclark@freedesktop.org>	freedreno/query: add optional enable hook Add enable hook for hw query providers. Some will need to configure perfctr selector registers, which we want to do at the start of the submit. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
6062941e4dd441bb67d5db760b87ffc0509befb7	18-Jan-2016	Rob Clark <robclark@freedesktop.org>	freedreno: per-generation OUT_IB packet Some a4xx firmware doesn't implement the "PFD" (prefetch-disabled) version of the CP_INDIRECT_BUFFER packet. So allow for PFD vs PFE per generation. Switch a3xx and a4xx over to using prefetch-enabled version (which is also what blob does.. it seems only on a2xx we cannot use PFE). Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
020009f7ccdffa84c6e1649c4e915954f5fd7cc0	19-Dec-2015	Marek Olšák <marek.olsak@amd.com>	u_upload_mgr: pass alignment to u_upload_alloc manually The fixed alignment of u_upload_mgr will go away. This is the first step. The motivation is that one u_upload_mgr can have multiple users, each allocating from the same buffer, but requiring a different alignment. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
e677b3047be30c0990ce72e5debb19c1f5627fc4	13-Dec-2015	Rob Clark <robclark@freedesktop.org>	freedreno/a4xx: fix fragcoord.z + fragdepth It seems like disabling earlyz on a4xx also, by defaults, disables fragcoord.z to the FS. For frag shaders that both read fragcoord(.z) and write fragdepth, we need to set some extra bits to prevent a lockup. This lets us get rid of the hack of disabling fragcoord.z (which prevented 0ad from lockups, but resulted in rendering corruption). Also fixes fbo-depth-sample-compare. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
9761d5146fa76dbb03da0ba94beba4c249f061d1	22-Nov-2015	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/a4xx: re-emit program on dirty framebuffer The program emit depends on certain fb details. Make sure those get updated when the fb changes. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
81b16350fa2e7c1b47d976be12d2313283f22e24	22-Nov-2015	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/a4xx: use a factor of 32767 for snorm8 blending It appears that the hardware wants the integer to be scaled the same way that the hardware representation is. snorm16 uses one of the float factors, so this is only relevant for snorm8. This fixes a number of subcases of bin/fbo-blending-formats GL_EXT_texture_snorm Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: mesa-stable@lists.freedesktop.org /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
6f17f19b17d6150788e713f92f6a05ef410c4060	22-Nov-2015	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/a4xx: only compute texture offset once for the view Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
f10bb0ac9ea558efe7b6dccd673eb2b6604119db	22-Nov-2015	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/a4xx: add ARB_texture_view support Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
99f12a3f1a825c53d790f12dae114f388bb6244c	21-Nov-2015	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/a4xx: add ARB_texture_buffer_range support Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
d4c40f99ab9b8ccf807cea45599231c0072f740b	21-Nov-2015	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/a4xx: add polygon mode support Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
22aeb0c5684cec11fd8cb4a159b10edbcfe8d6ec	21-Nov-2015	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/a4xx: disable blending and alphatest for integer rt0 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: mesa-stable@lists.freedesktop.org /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
f54c89f13e6c4759854d0b40b2b9bbac04dde5be	21-Nov-2015	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/a4xx: set fetchsize in mem2gmem texture restore Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
740eb63aa78a48bae5248b72f023d725ed82d1b3	21-Nov-2015	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/a4xx: fix 3d texture setup Same fix as on a3xx - set the second (tiny) layer size bitfield to the smallest level's size so that the hw knows not to minify beyond that. This fixes texelFetch sampler3D piglits. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: mesa-stable@lists.freedesktop.org /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
ec106e9f621cc1f8b3c1ee55aafa69d5ad159276	20-Nov-2015	Ilia Mirkin <imirkin@alum.mit.edu>	freedreno/a4xx: fix dst_alpha blend for RGBX render targets There are not native RGBX render formats, so we must manually force dst_alpha to be one, same as for a3xx. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
8106fec74c4d8548974fcf64e052a6bac07e926f	16-Nov-2015	Rob Clark <robclark@freedesktop.org>	freedreno/a3xx+a4xx: fix for stk binning pass hang We'd end up in a state where shader uses no inputs, yet num_elements is greater than zero. Triggered by a TF vertex shader which did: gl_Position = vec4(0.0, 0.0, 0.0, 0.0); resulting in a binning pass variant with no inputs. Includes equiv fix in a4xx, even though we don't have binning-pass enabled yet on a4xx. Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
6459e780ae44d8826322e0dc2466d0ee6d9e9800	27-Oct-2015	Rob Clark <robclark@freedesktop.org>	freedreno/a4xx: fix blend color Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
7465e161248b94d0bd1cdae6fc4c501ecfcf9b0b	27-Oct-2015	Rob Clark <robclark@freedesktop.org>	freedreno: update generated headers Signed-off-by: Rob Clark <robclark@freedesktop.org> /external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_emit.c