| 728e2c4d38b2c03ad1fdc997bef70e646ada9fe4 |
|
23-Nov-2016 |
Rob Clark <robdclark@gmail.com> |
freedreno/ir3: don't offset inloc by 8
On a3xx/a4xx, the SP_VS_VPC_DST_REG.OUTLOCn is offset by 8, so we used
to add this offset into fs->inputs[n].inloc. But a5xx drops this extra
offset-by-8. So instead make inloc zero based and add the offset when
we emit OUTLOCn values (for the gen's that need the offset).
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 98c83b5d1c865ecac2f1e8c7b6e8a092b3f351fa |
|
23-Nov-2016 |
Rob Clark <robdclark@gmail.com> |
freedreno/a4xx: use new shader linkage helper
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| ac1181ffbef5250cb3b651e047cce5116727c34c |
|
07-Jul-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
compiler: Rename INTERP_QUALIFIER_* to INTERP_MODE_*.
Likewise, rename the enum type to glsl_interp_mode.
Beyond the GLSL front-end, talking about "interpolation modes" seems
more natural than "interpolation qualifiers" - in the IR, we're removed
from how exactly the source language specifies how to interpolate an
input. Also, SPIR-V calls these "decorations" rather than "qualifiers".
Generated by:
$ find . -regextype egrep -regex '.*\.(c|cpp|h)' -type f -exec sed -i \
-e 's/INTERP_QUALIFIER_/INTERP_MODE_/g' \
-e 's/glsl_interp_qualifier/glsl_interp_mode/g' {} \;
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 80c288603300a06ac1585769cc491711c3d1b4f0 |
|
02-Jun-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: silence coverity warning
CID 1362451
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 1f2bc64f31872f04c27f9aa7a93e63a0091aaabf |
|
03-May-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: deal with VS which do not write position
Fixes $piglit/bin/glsl-1.40-tf-no-position
a3xx may need similar?
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 663c0e5155e9916b10163c102f0ece4eda5c3154 |
|
24-Apr-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: use pipe_debug_callback for shader-db traces
For multi-threaded shader-db support.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| f68c6951b86ac38ebdb89bc6b5a6285433e684a6 |
|
05-Mar-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: hw binning
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| dd9135c452a2a457fb6cabf7de573075d22a869a |
|
07-Mar-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: move where we deal w/ binning FS
Move where we pick dummy FS for binning pass, so the whole driver sees
the same dummy/no-op FS stage.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| c4ae047cabd8f7ef8ff90add285804635d8e0c50 |
|
01-Mar-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: enable shareable shaders
Now that we are no longer using the pctx reference in the shader, drop
it and turn on shareable shaders.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 805e080ba0ef637cfc7b637538b5a0ce5f0b53dc |
|
18-Jan-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: use smaller threadsize for more registers
Once we go past half of the "GPR" register file, it seems like we need
to run frag shader with smaller threadsize. (The vertex shader already
runs at TWO_QUADS, which is the minimum.)
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| e677b3047be30c0990ce72e5debb19c1f5627fc4 |
|
13-Dec-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: fix fragcoord.z + fragdepth
It seems like disabling earlyz on a4xx also, by defaults, disables
fragcoord.z to the FS. For frag shaders that both read fragcoord(.z)
and write fragdepth, we need to set some extra bits to prevent a
lockup.
This lets us get rid of the hack of disabling fragcoord.z (which
prevented 0ad from lockups, but resulted in rendering corruption). Also
fixes fbo-depth-sample-compare.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 57fc0dd8d5610a0a25cece53b172b0c992421db0 |
|
26-Nov-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: assign varying locations later
Rather than assigning inloc up front, when we don't yet know if it will
be unused, assign it last thing before the legalize pass.
Also, realize when inputs are unused (since for frag shader's we can't
rely on them being removed from ir->inputs[]). This doesn't make sense
if we don't also dynamically assign the inloc's, since we could end up
telling the hw the wrong # of varyings (since we currently assume that
the # of varyings and max-inloc are related..)
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 2fbe4e7d2fdb18e12860cd577990ec97b5e18647 |
|
26-Nov-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: rework vinterp/vpsrepl
Same as previous commit, for a4xx.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| ff9450ecd1f7635f8917e3177f0ef18eb8f9f49b |
|
21-Nov-2015 |
Ilia Mirkin <imirkin@alum.mit.edu> |
freedreno/a4xx: point regid to "red" even for alpha-only rb formats
Looks like a4xx hw does this in a more standard way and we don't need to
hack around it like we do on a3xx. Fixes GL_ALPHA formats in
fbo-blending-formats, fbo-colormask-formats, and fbo-alphatest-formats.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| c4572b7dfe7a4ae9dc6e900f89786fa9cf7769df |
|
11-Sep-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: convert from tgsi semantic/index to varying-slot
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| e523f69b1d2f0cb3ff7659e3c55b9a2e40240c9c |
|
10-Sep-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: switch to shader_enums.h interp constants
A small step towards un-TGSI'ifying ir3.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 868b66fce7a156efda840c00088f89f4ba6163c9 |
|
13-Aug-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: fix srgb render targets
Also fixes mipmap level generation for srgb textures.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 8885f2befaea68ce7f9d550c9b9ff5ae77524406 |
|
11-Aug-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: point-size and spritelist fixes
a4xx needs similar treatment as 995f55a6
Also fixup a few point-size and vpsrepl issues and drop fix_blit_fp()
hack previously needed for mem2gmem.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 2d6a889e8b786cd76d6711627c10be50615c2b62 |
|
09-Aug-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: fix vpsrepl for blit shaders
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 054526e49abb5e7fd49fed6f589cff6f1ab4c9f6 |
|
31-Jul-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: MRT support
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 0815729d964f4e8e6e263acf70b5b91577de027a |
|
23-Jul-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: bit of shader API refactoring
Since for transform-feedback, we'll need more than just the TGSI
tokens from the state object, just pass the entire state object to
ir3_shader_create(). This also cleans things up a bit for some
day in the future when we could take shader either as TGSI or
directly NIR (for ex, glsl2nir or spirv2nir paths). In the same
spirit, drop extra args from ir3_compile_shader_nir() (since it
can anyways get what it needs from the ir3_shader_variant).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| cb24d3b7ad2f6c03edd86d827db2b308670ae8a7 |
|
22-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno: misc minor cleanups
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 1b58d8c2bf6136af2a89178f9da4e5f0631d2909 |
|
22-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: (partial) gl_FragCoord.zw
The bit to enable .z is still commented out, as it is triggering gpu
hangs in 0ad. But at least gl_FragCoord.w works now, and we know what
bits we are *supposed* to set for .z (with that uncommented all piglit
fragcoord tests are passing).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| e5e11b5baf26e175f802c8078db92fd8492aa29d |
|
12-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: support for large shaders
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 20ea698c492ea04f52e50974ecf39e887d144e43 |
|
12-Apr-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 6f4c1976f4e5ecdebfe5b9ac16b6d13a5e60eed1 |
|
01-Apr-2015 |
Ilia Mirkin <imirkin@alum.mit.edu> |
freedreno: convert blit program to array for each number of rts
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 8efa3e340d13a9f373e7b2834f12d9fae43e6867 |
|
30-Mar-2015 |
Ilia Mirkin <imirkin@alum.mit.edu> |
freedreno: remove alpha key from ir3_shader
This complication is unnecessary and makes MRTs more complicated and
likely to generate tons of variants.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| bdf023482a6fd07adef090fb66a4aaaac22810fc |
|
21-Feb-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: bit of cleanup
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 69d23809d06cb1bb20a92430e18720baff5994bc |
|
07-Dec-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: frag-coord / face fixes
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 6a5ba23fa6156abb7d643080e2a2b477aa1ed559 |
|
06-Dec-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: temp hack for FLAT varyings
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 8ecbcbf0aab60e044dc4a9dabef2bdfb8db5abe9 |
|
05-Dec-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| e9589a8fcf60f9d04ea31e6f84f43f9d10a636da |
|
04-Dec-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: fd4_util -> fd4_format
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| c74f2db0a5dd35845727987b1cbd07c0cdab9678 |
|
03-Dec-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: frag-depth fixes
Also seems to fix kill/discard.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 3e698ebf44b443f28badf7443cf9516fc404871d |
|
29-Nov-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: add render target format to fd4_emit
This lets us move emitting SP_FS_MRT_REG back to fd4_program_emit.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 0c6275300e7eeee347cecc3f41d1a62f9e0592ef |
|
15-Nov-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: move where SP_FS_MRT_REGn is emitted
Addition of color fmt bitfield to this register (compared to a3xx) means
we need to re-emit if either prog or framebuffer state is dirty.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|
| 61c68b69d704b5faa5ff9d2b73b24bebf7e19412 |
|
31-Jul-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno: add adreno 420 support
Very initial support. Basic stuff working (es2gears, es2tri, and maybe
about half of glmark2). Expect broken stuff. Still missing: mem->gmem
(restore), queries, mipmaps (blob segfaults!), hw binning, etc.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/fd4_program.c
|