| b48fde15767284814b3df6e9d7946ca7f5eccbfb |
|
09-Jan-2017 |
Rob Clark <robdclark@gmail.com> |
freedreno/a5xx: use the non-_ZERO_BASE for vertexid
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| ec01ef2db187bfb2af4ce264c2f3ed24bbf005b4 |
|
26-Dec-2016 |
Rob Clark <robdclark@gmail.com> |
freedreno/ir3: fix linkage::var size
It should actually be 32 for a4xx/a5xx.. we still only advertise 16 but
for a5xx the linkage map includes position/psize.
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| fc10dc9fdea6ad7d04dfcdb8fd2e2d59ea67f68b |
|
22-Dec-2016 |
Rob Clark <robdclark@gmail.com> |
freedreno/ir3: rework location of driver constants
Rework how we lay out driver constants (driver-params, UBO/TFBO buffer
addresses, immediates) for more flexibility. For a5xx+ we need to deal
with the fact that gpu ptrs are 64b instead of 32b, which makes the
fixed offset scheme not work so well. While we are dealing with that
we might also make the layout more dynamic to account for varying # of
UBOs, etc.
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 728e2c4d38b2c03ad1fdc997bef70e646ada9fe4 |
|
23-Nov-2016 |
Rob Clark <robdclark@gmail.com> |
freedreno/ir3: don't offset inloc by 8
On a3xx/a4xx, the SP_VS_VPC_DST_REG.OUTLOCn is offset by 8, so we used
to add this offset into fs->inputs[n].inloc. But a5xx drops this extra
offset-by-8. So instead make inloc zero based and add the offset when
we emit OUTLOCn values (for the gen's that need the offset).
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 1be5670c8de8fd0488ba7a6152860968b02121b4 |
|
23-Nov-2016 |
Rob Clark <robdclark@gmail.com> |
freedreno/ir3: add new helper for shader linkage
Helps simplify things on a5xx, where pos/psize get added to the vs-out
map. And anyways, simplifies a3xx and a4xx.
Signed-off-by: Rob Clark <robdclark@gmail.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 83d7230fd5ab69e7e111e3a02e604e65922fb171 |
|
20-Aug-2016 |
Ilia Mirkin <imirkin@alum.mit.edu> |
a3xx: make use of software clipping when hw can't handle it
The hw clipper only handles up to 6 UCPs. If there are more than 6 UCPs,
or a clip vertex, or clip distances are in use, then we must use the
fallback discard-based clipping from the frag shader.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| ac1181ffbef5250cb3b651e047cce5116727c34c |
|
07-Jul-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
compiler: Rename INTERP_QUALIFIER_* to INTERP_MODE_*.
Likewise, rename the enum type to glsl_interp_mode.
Beyond the GLSL front-end, talking about "interpolation modes" seems
more natural than "interpolation qualifiers" - in the IR, we're removed
from how exactly the source language specifies how to interpolate an
input. Also, SPIR-V calls these "decorations" rather than "qualifiers".
Generated by:
$ find . -regextype egrep -regex '.*\.(c|cpp|h)' -type f -exec sed -i \
-e 's/INTERP_QUALIFIER_/INTERP_MODE_/g' \
-e 's/glsl_interp_qualifier/glsl_interp_mode/g' {} \;
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 2f1581059b31a99e8f15dff6339a4bd80baebe1b |
|
21-Mar-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: disable TGSI specific hacks in nir case
When we got NIR directly from state tracker (vs using tgsi_to_nir) we
need to realize this and skip some TGSI specific hacks.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 663c0e5155e9916b10163c102f0ece4eda5c3154 |
|
24-Apr-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: use pipe_debug_callback for shader-db traces
For multi-threaded shader-db support.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| e04db879f8933915501bfb9cce0d1359d62766bd |
|
25-Apr-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: handle color clamp variant ourselves
Now that there is a pass to do this in NIR, lets just use that and
manage the variants ourself, rather than letting state-tracker do it.
This way, mesa/st will precompile shaders without requiring
ST_DEBUG=precompile (which requires a debug build).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| adf795432f788b33822d3a94b704be4ca536c8f1 |
|
19-Apr-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: better workaround for astc+srgb
This *seems* like a hw bug, and maybe only applies to certain a4xx
variants/revisions. But setting the SRGB bit in sampler view state
(texconst0) causes invalid alpha for ASTC textures. Work around this
setting up a second texture state and using that to sample alpha
separately.
This way, srgb->linear conversion happens in hw *prior* to
interpolation.
This fixes 546 dEQP tests: dEQP-GLES3.functional.texture.*astc*srgb*
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| a148300b13fbda239146c163549868cc903c0a70 |
|
22-Apr-2016 |
Rob Clark <robclark@freedesktop.org> |
Revert "freedreno/a4xx: lower srgb in shader for astc textures"
Better workaround in the following patch.
This reverts commit 899bd63acefd49a668e11c42d2ad92fa55aa157d.
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 899bd63acefd49a668e11c42d2ad92fa55aa157d |
|
19-Apr-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: lower srgb in shader for astc textures
This *seems* like a hw bug, and maybe only applies to certain a4xx
variants/revisions. But setting the SRGB bit in sampler view state
(texconst0) causes invalid alpha for ASTC textures. Work around this
by doing the srgb->linear conversion in the shader instead.
This fixes 392 dEQP tests: dEQP-GLES3.functional.texture.*astc*srgb*
(The remaining fails seem to be a bug w/ ASTC + linear filtering, also
possibly a420.0 specific.)
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 5b955f09f72b2217576ea8980a3d8fd3ba63854a |
|
07-Mar-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: constify the shader variants
Most of the driver just needs read-only access, so constify..
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| c4ae047cabd8f7ef8ff90add285804635d8e0c50 |
|
01-Mar-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: enable shareable shaders
Now that we are no longer using the pctx reference in the shader, drop
it and turn on shareable shaders.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| c3f2f8cbe47a51087dcc82826bd939786c812366 |
|
01-Mar-2016 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: pass ctx to constant-emit code
Rather than fishing it out of the shader. This removes the other big
user of shader->pctx.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 1a882fd2ee84ae28a06cf07902dc4645d8ad4a6d |
|
18-Jan-2016 |
Emil Velikov <emil.velikov@collabora.com> |
nir: move shader_enums.[ch] to compiler
This way one can reuse it in glsl, nir or other infrastructure without
pulling nir as dependency.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 74135f804a4f18040a0a62664df67d35c8090d1d |
|
24-Oct-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: refactor NIR IR handling
Immediately convert into NIR and do an initial key-agnostic lowering/
optimization pass. This should let us share most of the per-variant
transformations between each variant, and hopefully minimize the draw-
time variant creation part of the compilation process.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 57fc0dd8d5610a0a25cece53b172b0c992421db0 |
|
26-Nov-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: assign varying locations later
Rather than assigning inloc up front, when we don't yet know if it will
be unused, assign it last thing before the legalize pass.
Also, realize when inputs are unused (since for frag shader's we can't
rely on them being removed from ir->inputs[]). This doesn't make sense
if we don't also dynamically assign the inloc's, since we could end up
telling the hw the wrong # of varyings (since we currently assume that
the # of varyings and max-inloc are related..)
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 8106fec74c4d8548974fcf64e052a6bac07e926f |
|
16-Nov-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a3xx+a4xx: fix for stk binning pass hang
We'd end up in a state where shader uses no inputs, yet num_elements is
greater than zero. Triggered by a TF vertex shader which did:
gl_Position = vec4(0.0, 0.0, 0.0, 0.0);
resulting in a binning pass variant with no inputs.
Includes equiv fix in a4xx, even though we don't have binning-pass
enabled yet on a4xx.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| c9b982b72d443b138cfbded2f40350771c0bb321 |
|
09-Oct-2015 |
Rob Clark <robclark@freedesktop.org> |
glsl: move shader_enums into nir
First step towards inverting the dependency between glsl and nir (so nir
can be used without glsl). Also solves this issue with 'make distclean'
Making distclean in mesa
make[2]: Entering directory '/mnt/sdb1/Src64/Mesa-git/mesa/src/mesa'
Makefile:2486: ../glsl/.deps/shader_enums.Plo: No such file or directory
make[2]: *** No rule to make target '../glsl/.deps/shader_enums.Plo'. Stop.
make[2]: Leaving directory '/mnt/sdb1/Src64/Mesa-git/mesa/src/mesa'
Makefile:684: recipe for target 'distclean-recursive' failed
make[1]: *** [distclean-recursive] Error 1
make[1]: Leaving directory '/mnt/sdb1/Src64/Mesa-git/mesa/src'
Makefile:615: recipe for target 'distclean-recursive' failed
make: *** [distclean-recursive] Error 1
Reported-by: Andy Furniss <adf.lists@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 91ec210ea8e35af8a7b30fa599b67b1faa55f34c |
|
10-Sep-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: add support for ucp
Use nir_lower_clip pass for adding the VS/FS instructions to handle
user-clip-planes and CLIPDIST. Wire up support for load_user_clip_plane
intrinsic to fetch ucp[plane] values as driver-params (passed as const's
to the shader).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| c4572b7dfe7a4ae9dc6e900f89786fa9cf7769df |
|
11-Sep-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: convert from tgsi semantic/index to varying-slot
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| e523f69b1d2f0cb3ff7659e3c55b9a2e40240c9c |
|
10-Sep-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: switch to shader_enums.h interp constants
A small step towards un-TGSI'ifying ir3.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 8885f2befaea68ce7f9d550c9b9ff5ae77524406 |
|
11-Aug-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a4xx: point-size and spritelist fixes
a4xx needs similar treatment as 995f55a6
Also fixup a few point-size and vpsrepl issues and drop fix_blit_fp()
hack previously needed for mem2gmem.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 98a4b111fbb9e3ae45e907ddd4d2407e5ab669ec |
|
25-Jul-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: add transform-feedback support
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| a240748de52f2e469e91b60d29ae872828a594d7 |
|
25-Jul-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: cleanup driver-param stuff
Add 'enum ir3_driver_param' to track driver-param slots, and a
create_driver_param() helper to avoid having the knowledge about
where driver params are placed in const regs spread throughout
the code as we add additional driver-params.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 65d36a109a7dd333c15180a0f30ad919eb01d78f |
|
24-Jul-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a3xx+a4xx: add support for vtxcnt semantic
This will be used for stream-out (transform-feedback)
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 56462a30080c1f25a81ae566d59a25d2ad6bb809 |
|
24-Jul-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: move emit_const to ir3
Details of the cmdstream packets are different between a3xx and a4xx,
but the logic about the layout of const registers is the same, as that
is dictated by the ir3 shader compiler. So rather than duplicating
logic that is tightly coupled to ir3 between a3xx and a4xx, move this
into ir3 and use per-generation callbacks for to build the cmdstream
packets.
This should make it easier to pass additional const regs (such as for
transform feedback). And it also keeps the layout internal to ir3 in
case we want to make the layout more dynamic some day.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 0815729d964f4e8e6e263acf70b5b91577de027a |
|
23-Jul-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: bit of shader API refactoring
Since for transform-feedback, we'll need more than just the TGSI
tokens from the state object, just pass the entire state object to
ir3_shader_create(). This also cleans things up a bit for some
day in the future when we could take shader either as TGSI or
directly NIR (for ex, glsl2nir or spirv2nir paths). In the same
spirit, drop extra args from ir3_compile_shader_nir() (since it
can anyways get what it needs from the ir3_shader_variant).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 65b2ae510bb07b75f583ecedfd59766621e1cb43 |
|
06-Jul-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: shader-db traces
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| db5105b4b35e064f3934154b45de15422a1bdb0a |
|
29-Jun-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: add ir3_shader_disasm()
Split out most of dump_info() from ir3_cmdline compiler into a function
that can be used both by cmdline compiler and also for the disasm debug
option. This way, for FD_MESA_DEBUG=disasm we also get to see intput/
output registers, etc.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 0f008082b184072159e5aedc7fc103efba8740ed |
|
08-Jun-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno: remove int sampler shader variants
We get this information from NIR (which gets it from sview decl in tgsi
when translating from tgsi), so no need to maintain shader variants for
this.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 694beb8b830c993e9bfb744655be3dbd558ab3a8 |
|
23-May-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: introduce ir3_compiler object
Right now, just provides a cleaner way to get at the gpu-id, given the
separation between compiler and context. But we will need this also to
hold the reg-set for new register allocation.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| d13803c76fd7429df64c1aa3631dcc451e7f1a29 |
|
30-Mar-2015 |
Ilia Mirkin <imirkin@alum.mit.edu> |
freedreno/ir3: add support for FS_COLOR0_WRITES_ALL_CBUFS property
This will enable the driver to tell which regids to link up to which
MRT outputs.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 8efa3e340d13a9f373e7b2834f12d9fae43e6867 |
|
30-Mar-2015 |
Ilia Mirkin <imirkin@alum.mit.edu> |
freedreno: remove alpha key from ir3_shader
This complication is unnecessary and makes MRTs more complicated and
likely to generate tons of variants.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| e9f2abe349886ae5423c7c31d201e7d587a3695a |
|
25-Feb-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: handle flat bypass for a4xx
We may not need this for later a4xx patchlevels, but we do at least need
this for patchlevel 0. Bypass bary.f for fetching varyings when flat
shading is needed (rather than configure via cmdstream). This requires
a special dummy bary.f w/ (ei) flag to signal to scheduler when all
varyings are consumed. And requires shader variants based on rasterizer
flatshade state to handle TGSI_INTERPOLATE_COLOR.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| f6b2e8af7425c67f8def9dfba92f6f0ad9585b40 |
|
02-Oct-2014 |
Ilia Mirkin <imirkin@alum.mit.edu> |
freedreno/a3xx: add support for vertexid and instanceid sysvals
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| e7026ac486c157b419726e6238d880a83172484d |
|
04-Jan-2015 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: fix pos_regid > max_reg
We can't (or don't know how to) turn this off. But it can end up being
stored to a higher reg # than what the shader uses, leading to
corruption.
Also we currently aren't clever enough to turn off frag_coord/frag_face
if the input is dead-code, so just fixup max_reg/max_half_reg. Re-org
this a bit so both vp and fp reg footprint fixup are called by a common
fxn used also by ir3_cmdline. Also add a few more output lines for
ir3_cmdline to make it easier to see what is going on.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| eb6fd3b8eb9c19bb501a091d1696e5db1ac4c690 |
|
06-Dec-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: lower TXP as needed
On a3xx, lower TXP for 3D textures, on a4xx lower all TXP.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 82104c19f304a0e953172ad61d149640f0512fa0 |
|
30-Nov-2014 |
Ilia Mirkin <imirkin@alum.mit.edu> |
freedreno/a3xx: enable sampling from integer textures
We need to produce a u32 destination type on integer sampling
instructions, so keep that in a shader key set based on the
currently-bound textures.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
|
| 61c68b69d704b5faa5ff9d2b73b24bebf7e19412 |
|
31-Jul-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno: add adreno 420 support
Very initial support. Basic stuff working (es2gears, es2tri, and maybe
about half of glmark2). Expect broken stuff. Still missing: mem->gmem
(restore), queries, mipmaps (blob segfaults!), hw binning, etc.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
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| 82103206feb10b3cfc581fe5ea88673e4d53b744 |
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05-Nov-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: move some helpers
Split out a few helpers from fd3_program so we don't have to duplicate
for fd4_program.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
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| 3fcb0212018e52c374f937e806abeca07e938d28 |
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18-Oct-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a3xx: disable early-z when we have kill's
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
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| 368466b7b72aed74b917aeb3225d7a0a7101678c |
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14-Oct-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: optimize shader key comparision
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
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| d595987ea3d1706fecb9f6416031ec8b27c95a9e |
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14-Oct-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a3xx: refactor/optimize emit
Because we reuse various bits of emit code (for state/vertex/prog/etc)
for both regular draws and internal draws (gmem<->mem, clear, etc), the
number of parameters getting passed around has been growing. Refactor
to group these into fd3_emit. This simplifies fxn signatures, avoids
passing around shader key on the stack, etc. It also gives us a nice
place to cache shader-variant lookup to avoid looking up shader variants
multiple times per draw (without having to *also* pass them around as
fxn args everywhere).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
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| 7cdd4679943a72b97aad1c584da4bcb0e1f003f2 |
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29-Sep-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a3xx: add support to emulate GL_CLAMP
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
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| ed48f91275f52f26b513fc2970233063bfa023af |
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26-Sep-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a3xx: add flat interpolation mode
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
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| 80058c0f08ea94d3de96909027a792e397fa9262 |
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12-Sep-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/a3xx: alpha render-target shenanigans
We need the .w component to end up in .x, since the hw appears to fetch
gl_FragColor starting with the .x coordinate regardless of MRT format.
As long as we are doing this, we might as well throw out the remaining
unneeded components.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
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| db193e5ad06e7a2fbcffb3bb5df85d212eb12291 |
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25-Jul-2014 |
Rob Clark <robclark@freedesktop.org> |
freedreno/ir3: split out shader compiler from a3xx
Move the bits we want to share between generations from fd3_program to
ir3_shader. So overall structure is:
fdN_shader_stateobj -> ir3_shader -> ir3_shader_variant -> ir3
|- ...
\- ir3_shader_variant -> ir3
So the ir3_shader becomes the topmost generation neutral object, which
manages the set of variants each of which generates, compiles, and
assembles it's own ir.
There is a bit of additional renaming to s/fd3_compiler/ir3_compiler/,
etc.
Keep the split between the gallium level stateobj and the shader helper
object because it might be a good idea to pre-compute some generation
specific register values (ie. anything that is independent of linking).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/gallium/drivers/freedreno/ir3/ir3_shader.h
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