Cross Reference: /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit

History log of /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
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dd39e487261990a7e7ac699d004e64dda48f08d8	15-Jan-2017	Ilia Mirkin <imirkin@alum.mit.edu>	nvc0/ir: emit FMZ flag when requested on FFMA Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
84e946380b2d5ddc62a107b667be39abf1932704	26-Oct-2016	Samuel Pitoiset <samuel.pitoiset@gmail.com>	nvc0/ir: fix emission of IMAD with NEG modifiers The emitter tried to emit sub instead of subr when src0 has actually a NEG modifier. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: "11.0 12.0 13.0" <mesa-stable@lists.freedesktop.org> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
1ec7227d44dceae8de7b93f846bbd33d66007909	21-Oct-2016	Samuel Pitoiset <samuel.pitoiset@gmail.com>	nvc0/ir: fix emission of SHLADD with NEG modifiers This affects GF100:GK110 chipsets, but not GM107+ where the logic is a bit different. The emitters tried to emit sub instead of subr when src0 has a NEG modifier. This fixes the following piglit tests glsl-fs-loop-nested and glsl-vs-loop-nested. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Acked-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: "13.0" <mesa-stable@lists.freedesktop.org> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
6e08f3e96c6c3f269ea3ee79bb7e10940e6a13be	21-Oct-2016	Samuel Pitoiset <samuel.pitoiset@gmail.com>	nvc0/ir: remove outdated comment about SHLADD Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
31545b64b80aa939a693723e07f06fe45160ae62	15-Sep-2016	Samuel Pitoiset <samuel.pitoiset@gmail.com>	nvc0/ir: add emission for SHLADD Unfortunately, we can't use the emit helpers for GF100/GK110 because src1 and src2 are swapped. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
50baaf6bc624e78f6d92f2316a370e11d4c4d882	15-Sep-2016	Samuel Pitoiset <samuel.pitoiset@gmail.com>	nvc0/ir: fix subops for IMAD Offset was wrong, it's at bit 8, not 4. Also, uses subr instead of sub when src2 has neg. Similar to GK110 now. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: mesa-stable@lists.freedesktop.org /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
e0a067ed484698ff62dd8c8750aeb46f18988b17	25-Aug-2016	Samuel Pitoiset <samuel.pitoiset@gmail.com>	nv50/ir: always emit the NDV bit for OP_QUADOP This silences a divergent error found with F1 2015. Basically, the NDV bit has to be set when a FSWZ instruction is inside divergent code, but it's not needed otherwise. The correct fix should be to set it only in divergent code situations. GM107 emitter already sets that bit. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: <mesa-stable@lists.freedesktop.org> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
3a2e67bf781d88253d81b20de72ce22acf75916d	23-Jul-2016	Samuel Pitoiset <samuel.pitoiset@gmail.com>	nvc0/ir: fix up an assertion in emitUADD() It's illegal to have neg modifiers on both sources for OP_ADD, and it's illegal to have OP_SUB with just src0 neg. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
704bc0f0e98f3bbdef33cad12646d4e1bf01e8aa	29-May-2016	Ilia Mirkin <imirkin@alum.mit.edu>	nvc0: add support for VOTE tgsi opcodes Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
4b1a167a2bce936beabd03ffc313a63d8deeed09	30-May-2016	Ilia Mirkin <imirkin@alum.mit.edu>	nvc0/ir: fix spilling predicates to registers Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
8cc80e396e0f604bdeb962fe35c32ca1e6b361f3	29-May-2016	Ilia Mirkin <imirkin@alum.mit.edu>	nvc0/ir: fix emission of predicate spill to register The lane mask only applies to real mov's, while here we're using PSET. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
df2881381ac67c42aa8ec9e0ed28f21a1d253785	26-May-2016	Ilia Mirkin <imirkin@alum.mit.edu>	nvc0/ir: handle a load's reg result not being used for locked variants For a load locked, we might not use the first result but the second result is the predicate result of the locking. In that case the load splitting logic doesn't apply (which is designed for splitting 128-bit loads). Instead we take the predicate and move it into the first position (as having a dead result in first def's position upsets all sorts of things including RA). Update the emitters to deal with this as well. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Tested-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
b663db44ba35c5499265fcc629c66a1acbaca3f5	27-Apr-2016	Samuel Pitoiset <samuel.pitoiset@gmail.com>	nvc0/ir: add emission for SULDB and SUSTx Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
cd88d1a171bf4493ddd5590c8a294543f14f19d5	27-Apr-2016	Samuel Pitoiset <samuel.pitoiset@gmail.com>	nvc0/ir: add emission for OP_SULEA Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
ba3f0b6d5920165c735d51500544da8c29b09060	09-Apr-2016	Ilia Mirkin <imirkin@alum.mit.edu>	nvc0: fix gl_SampleMaskIn computation The SAMPLEMASK semantic should only return the bits set covered by the current invocation. However we were always retrieving the covmask, which returns the covered samples of the whole pixel. When not doing per-sample invocation, this is precisely what we want. However when doing per-sample invocation, we have to select the sampleid'th bit and only return that. Furthermore, this means that we have to have a 1:1 correlation for invocations and samples. This fixes most dEQP-GLES31.functional.shaders.sample_variables.sample_mask_in.* tests. A few failures remain due to disagreements about nr_samples==1 logic as well as what happens with MSAA x2 RTs when the shading fraction is 0.5. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
f5fe9030021af830e6c4453f4ad1521cbb697c81	07-May-2016	Ilia Mirkin <imirkin@alum.mit.edu>	nv50/ir: generalize interp fixups to be able to fixup anything Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
3da8528846773e936850b51ae7d6287758c45b7b	26-Apr-2016	Samuel Pitoiset <samuel.pitoiset@gmail.com>	nvc0/ir: fix wrong emission of (a OP b) OP c The third source must be emitted at offset 49 instead of 17 and the not modifier is at 52 instead of 20. If you look a bit above in emitLogicOp() you will see that the dest is emitted at 17 which confirms that src(2) is obviously wrong. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
275019d7db033286e41eb4983ac50d3d3d335586	22-Feb-2016	Samuel Pitoiset <samuel.pitoiset@gmail.com>	nvc0/ir: fix wrong pred emission for ld lock on GK104 This fixes 84b9b8f (nvc0/ir: add missing emission of locked load predicate). Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
5777e87bed9de5db9ab08a1388265978507bc88e	07-Mar-2016	Samuel Pitoiset <samuel.pitoiset@gmail.com>	nvc0/ir: make sure that thread count immediate for BAR fit The limit of the thread count immediate value is 12 bits. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
07ed003faf3199a3e95852e7a34763aeaf76503d	28-Feb-2016	Samuel Pitoiset <samuel.pitoiset@gmail.com>	nv50/ir: emit VOTE instruction Changes from v2: - add missing NOT modifier for GK110/GM107 Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
84b9b8f0a395a26984980bb465b06ba08f55a1c6	22-Feb-2016	Samuel Pitoiset <samuel.pitoiset@gmail.com>	nvc0/ir: add missing emission of locked load predicate Like unlocked store on shared memory, locked store can fail and the second dest which is a predicate must be emitted. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: mesa-stable@lists.freedesktop.org /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
9f0d059d4bab97e334fb3fecc24a1421b562d9e5	21-Feb-2016	Samuel Pitoiset <samuel.pitoiset@gmail.com>	nvc0/ir: add ld lock/st unlock emission on GK104 Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
6526225f888a08b301e8c39ec70b4e739081e490	21-Feb-2016	Samuel Pitoiset <samuel.pitoiset@gmail.com>	nv50/ir: restore OP_SELP to be a regular instruction Actually OP_SELP doesn't need to be a compare instruction. Instead we just need to set the NOT modifier when building the instruction. While we are at it, fix the dst register type and use a GPR. Suggested by Ilia Mirkin. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
e0371e63df173be38a086a5d816eeaf0e8cbe7eb	05-Feb-2016	Samuel Pitoiset <samuel.pitoiset@gmail.com>	nv50/ir: make OP_SELP a compare instruction This OP_SELP insn will be used to handle compare and swap subops. Changes from v2: - fix logic for GK110+ Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
0c930557bf96721ce50ca95b5201be09da905cb8	25-Jan-2016	Samuel Pitoiset <samuel.pitoiset@gmail.com>	nv50/ir: add lock/unlock subops for load/store Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
ca23c8081f1f9f709df7a63b9e6de379c0b8df44	16-Feb-2016	Ilia Mirkin <imirkin@alum.mit.edu>	nv50/ir: fix quadop emission in the presence of predication When there's a predicate, it just goes onto the sources list. If the quadop only has a single regular source, we will end up thinking that the predicate is the second source. Check explicitly for the predSrc so that we don't accidentally emit the wrong thing. This fixes a bunch of dEQP-GLES3.functional.shaders.derivate.* tests. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: mesa-stable@lists.freedesktop.org /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
1a0fde1f52c59e0dbada03f387c8e25d9475ebbe	05-Feb-2016	Ilia Mirkin <imirkin@alum.mit.edu>	nvc0/ir: fix converting between predicate and gpr The spill logic will insert convert ops when moving between files. It seems like the emission logic wasn't quite ready for these converts. Tested on fermi, and visually looked at nvdisasm output for maxwell. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: mesa-stable@lists.freedesktop.org /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
df043f076464d817a9d88c4c43757e65b6eae3f9	11-Jan-2016	Ilia Mirkin <imirkin@alum.mit.edu>	nvc0/ir: fix atomic compare-and-swap arguments Teach the emitter that the two registers are sequential, and drop the second arg entirely, in favor of a double-wide first argument. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
34217018c4ae9c2c672534494be0c5b9569609e2	29-Oct-2015	Ilia Mirkin <imirkin@alum.mit.edu>	nvc0/ir: add support for PK2H/UP2H Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
b8c524ff88499f64c94f1d1c41671107f98f991a	29-Nov-2015	Samuel Pitoiset <samuel.pitoiset@gmail.com>	nv50/ir: always display the opcode number for unknown instructions This helps in debugging unknown instructions. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
8e68113c1a78c48f26e820f4beb2dda9e4b99f32	18-Nov-2015	Ilia Mirkin <imirkin@alum.mit.edu>	nvc0/ir: actually emit AFETCH on kepler Looks like this was forgotten in the commit which added the AFETCH logic. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: mesa-stable@lists.freedesktop.org /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
39f51ec96f00f601b9c4d4e321dacb3af9dc866f	14-Sep-2015	Ilia Mirkin <imirkin@alum.mit.edu>	nvc0/ir: add support for TGSI_SEMANTIC_HELPER_INVOCATION Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
12c850d01ce2bf364f2b1719154df789d43a7a59	05-Nov-2015	Hans de Goede <hdegoede@redhat.com>	nvc0/ir: Add support for double immediates Add support for encoding double immediates (up to 20 bits of precision) into the generated nvc0 machine-code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
b75fff70d82474a571c59c2a3a01e4f9f02286a7	21-Oct-2015	Ilia Mirkin <imirkin@alum.mit.edu>	nvc0: do upload-time fixups for interpolation parameters Unfortunately flatshading is an all-or-nothing proposition on nvc0, while GL 3.0 calls for the ability to selectively specify explicit interpolation parameters on gl_Color/gl_SecondaryColor which would override the flatshading setting. This allows us to fix up the interpolation settings after shader generation based on rasterizer settings. While we're at it, we can add support for dynamically forcing all (non-flat) shader inputs to be interpolated per-sample, which allows st/mesa to not generate variants for these. Fixes the remaining failing glsl-1.30/execution/interpolation piglits. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
63cb85e567ad1025ee990b38f43c2f1ef811821b	19-Aug-2015	Ilia Mirkin <imirkin@alum.mit.edu>	nvc0/ir: detect i2f/i2i which operate on specific bytes/words Some Unigine shaders have been observed to unpack bytes out of 32-bit integers and convert them to floats. I2F/I2I can handle this sort of thing directly. Detect the handleable situations. This misses 16-bit word capabilities in nv50, but I haven't seen shaders that would actually make use of that. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
2f5ee9bf27b912726dea969a5e5159e1d6665f6c	17-Aug-2015	Ilia Mirkin <imirkin@alum.mit.edu>	gk110/ir: fix sched calculator to consider all registers in the ISA GK110/GK208 have 256 registers, not 64. Find out the number of registers from the target to avoid unnecessary iteration for pre-GK110. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
ab63610a3603ae1e40a36d238b5938621bb9e8cc	28-Jul-2015	Ilia Mirkin <imirkin@alum.mit.edu>	nvc0/ir: fix barrier emission immediate arguments require a flag to be set for each one Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
9d60793a03e40e1d139b78fce0144cad57438741	24-Jul-2015	Ilia Mirkin <imirkin@alum.mit.edu>	nvc0/ir: kepler can't do indirect shader input/output loads directly There's a special AL2P instruction (called AFETCH in nv50 ir) which computes a "physical" value to be used with indirect addressing with ALD. Fixes tcs-input-array--index-rd tcs-output-array--index-wr varying-indexing tessellation tests on Kepler. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
e5ad19a46e87ed22943d7f6ad046f974fd5977e1	09-May-2015	Ilia Mirkin <imirkin@alum.mit.edu>	nvc0/ir: allow iset to produce a boolean float Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
0ec6b8ea8ce0929ecacf6edc8db198b7b9604f18	04-May-2015	Ilia Mirkin <imirkin@alum.mit.edu>	nvc0/ir: avoid jumping to a sched instruction Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp