History log of /external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
Revision Date Author Comments (<<< Hide modified files) (Show modified files >>>)
f519c47f7d47d88ecf3b5e8f28fdffaa12f684d3 16-Dec-2016 Samuel Pitoiset <samuel.pitoiset@gmail.com> nv50/ir: improve instruction pipelining on gm107

This makes use of scheduling control codes which are very useful
for improving the instruction pipelining.

This patch will increase performance on Maxwell GPUs by, at least,
x1.5 up to x3.5 for some benchmarks.

Although this has been fairly well tested, I would not be suprised
if someone hit a corner case somewhere. That way, the scheduler
is enabled by default but it can be deactivated by using
NV50_PROG_SCHED=0.

Thanks to Scott Gray for the reverse engineering work available from
https://github.com/NervanaSystems/maxas/wiki/Control-Codes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre Moreau <pierre.morrow@free.fr>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Tested-by: Jan Vesely <jan.vesely@rutgers.edu>
/external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
3ac373df6e47a65bdb5e5bda57dfc9f2a8010f53 21-Jul-2016 Samuel Pitoiset <samuel.pitoiset@gmail.com> gm107/ir: add a legalize SSA pass for PFETCH

PFETCH, actually ISBERD on GM107+ ISA only accepts a GPR for src0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
f97f755192210ce3690e67abccefa133d398d373 08-Dec-2015 Ilia Mirkin <imirkin@alum.mit.edu> nvc0/ir: fix up mul+add -> mad algebraic opt, enable for integers

For some reason this has been disabled for integers ever since codegen
was merged, despite there being emission code for IMAD. Seems to work.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
d548d47edf9f05e6dbf9656abc2f8e78d02cb2f6 09-May-2014 Ben Skeggs <bskeggs@redhat.com> nvc0: add maxwell (sm50) compiler backend

The big missing part here is proper sched data calculations, but
hopefully the chosen placeholder will be sufficient for now.

Passes piglit as well as GK107 does.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp