| 2b621c47aa515add6452a788c0c27067fc60be20 |
|
27-Dec-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: add new HUD query num-SDMA-IBs
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 6b8a371e00b715b630418ced2ee867e7b2f36b11 |
|
27-Dec-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: rename the num-ctx-flushes query to num-GFX-IBs
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 49fa4a4e600cbb35c43a85fab2ed4aac3e6acccf |
|
11-Nov-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: add RADEON_SURF_OPTIMIZE_FOR_SPACE
FORCE_TILING should disable it. It has no effect now, but that may change
soon.
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 7786f8c63564f1eb421a8636cdbd15c471ec8632 |
|
27-Oct-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: add enum radeon_micro_mode
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| bf4d102ea3419ade6759bf9c3ad9d40c7f9b3c27 |
|
26-Oct-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: add radeon_surf::is_linear
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| e9c76eeeaa673331fec6056a4baa30095de42f5e |
|
26-Oct-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: remove radeon_surf_level::pitch_bytes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 692f2640ab0c4c923a5ba12ff8526d2d1a3eefb1 |
|
26-Oct-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: replace radeon_surf_info::dcc_enabled with num_dcc_levels
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 2664351dfeeba2c1d0de272cdf6d5fd940a367e9 |
|
23-Oct-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: re-order radeon_surf::dcc and htile members
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 2a2e53757796b3fed3119cb033e5cf5144843850 |
|
23-Oct-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: rename bo_size -> surf_size, bo_alignment -> surf_alignment
these names were misleading.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 67a44c97afb72812639039eb4594592c91c9ead5 |
|
23-Oct-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: remove flags specific to libdrm_radeon from winsys interface
These just say whether libdrm can assume that the latest radeon_surface
definition is used by Mesa.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 7a706ad25cefc666b54ddf778d047691a575b689 |
|
23-Oct-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: remove r600_htile_info
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 7e73ff87c0255a8e0498a47991b640cdece35928 |
|
23-Oct-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: remove unnecessary fields from radeon_surf_level
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| d5c7ea3b83168d8fd77ed4bd834901209e1d47da |
|
23-Oct-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: decrease the size of radeon_surf
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| e9590d9092fbcd551f5597149c64016b6f861233 |
|
23-Oct-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: pass pipe_resource and other params to surface_init directly
This removes input-only parameters from the radeon_surf structure.
Some of the translation logic from pipe_resource to radeon_surf is moved to
winsys/radeon.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| ba174b8dfff0777075f62a9188124d0bb22a5f17 |
|
23-Oct-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: define RADEON_SURF_MODE_* as enums
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 81a95946dab730c1cfcf04ac1373cea5f7908f65 |
|
20-Oct-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: fold radeon_winsys::surface_best into radeon/winsys
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| d4d9ec55c589156df4edc227a86b4a8c41048d58 |
|
11-Oct-2016 |
Marek Olšák <marek.olsak@amd.com> |
radeonsi: implement TC-compatible HTILE
so that decompress blits aren't needed and depth texturing needs less
memory bandwidth.
Z16 and Z24 are promoted to Z32_FLOAT by the driver, because TC-compatible
HTILE only supports Z32_FLOAT. This doubles memory footprint for Z16.
The format promotion is not visible to state trackers.
This is part of TC-compatible renderbuffer compression, which has 3 parts:
DCC, HTILE, FMASK. Only TC-compatible FMASK compression is missing now.
I don't see a measurable increase in performance though.
(I tested Talos Principle and DiRT: Showdown, the latter is improved by
0.5%, which is almost noise, and it originally used layered Z16,
so at least we know that Z16 promoted to Z32F isn't slower now)
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| dfc1afda83a22d8e6b23f003748cd78fd089a0ac |
|
04-Oct-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
winsys/radeon: add buffer_get_reloc_offset
Really fix the bug that was supposed to be fixed by commits 3e7cced4b and
a48bf02d: even when virtual addresses are used, the legacy relocation-based
method with offsets relative to the kernel's buffer object are used for
video submissions.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97969
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| cfd870de70d437c0d62afb9eec675f81bf45be6a |
|
29-Sep-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
gallium/radeon: update documentation of buffer_get_virtual_address
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| de84e99e454adede4f95c1cfd59f24c9dcc4e73d |
|
27-Sep-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
gallium/radeon/winsyses: add radeon_winsys::min_alloc_size
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| a3832590c60e3016a94bbba79072b2913585a672 |
|
08-Sep-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
winsys/amdgpu: add fence and buffer list logic for slab allocated buffers
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 6d89a4067627fdf568c6c4e3d9a201fd45d5352b |
|
09-Sep-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
gallium/radeon: add RADEON_FLAG_HANDLE
When passed to winsys->buffer_create, this flag will indicate that we require
a buffer that maps 1:1 with a kernel buffer handle.
This is currently set for all textures, since textures can potentially be
exported to other processes. This is not a huge loss, since the main purpose
of this patch series is to deal with applications that allocate many small
buffers.
A hypothetical application with tons of tiny textures might still benefit
from not setting this flag, but that's not a use case I'm worried about
just now.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| e703f71ebdf91938c83f47c898f1da058ce0ac32 |
|
07-Sep-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
gallium/radeon: add RADEON_USAGE_SYNCHRONIZED
This is really the behavior we want most of the time, but having a
SYNCHRONIZED flag instead of an UNSYNCHRONIZED one has the advantage that
OR'ing different flags together always results in stronger guarantees.
The parent BOs of sub-allocated buffers will be added unsynchronized.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 17fff0c2dece289214499a5621ca29ca08e639f0 |
|
08-Sep-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
winsys/amdgpu: remove amdgpu_cs_lookup_buffer
The radeonsi driver doesn't and shouldn't care about the buffer index.
Only the virtual addresses matter.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| a86be7b6ad2b9b909202fa0653b96cffb3131137 |
|
02-Sep-2016 |
Dave Airlie <airlied@redhat.com> |
radeon: move radeon_family/chip_class defintions to common
This just moves these to a common header file.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 971ef7518fe06033222b53ea843792d3018c6ab2 |
|
18-Aug-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: add a driver query for AMDGPU_INFO_NUM_EVICTIONS
If the kernel driver doesn't support it, it returns 0.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| bcfd49e5119a0c315aebf4773e7c50fe282339b2 |
|
17-Aug-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: increase priority for shader binaries
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| c3f716fe6749c65c7a75e48b57d0bdccb93526ef |
|
17-Aug-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: merge USER_SHADER and INTERNAL_SHADER priority flags
there's no reason to separate these
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 1ac23a9359556091b12ed1345737084e3a2f6ae3 |
|
11-Aug-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: assign the highest priority to scratch; make rings second
just FYI, the kernel receives priority/4
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 9009516501c591c28121bac8dfbc0042ad51eceb |
|
11-Aug-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/winsys: re-number winsys priority flags
free 60..63, move CP_DMA up
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 95020c6dfd74d0ce35c0f0ce89f313ad266ba721 |
|
11-Aug-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: mark shader rings as highest-priority buffers
and rename the enum
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 1e04483c22e372aac8a664fe2b272b10aa774eea |
|
05-Aug-2016 |
Marek Olšák <marek.olsak@amd.com> |
winsys/amdgpu: track the amount of mapped memory
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| e0736c438c15f1793630424d29ef63868f12a172 |
|
28-Jul-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
winsys/amdgpu: query ME/PFP/CE firmware versions
The radeon kernel module doesn't have the firmware query interface, so the
corresponding values will remain 0.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 04a6cb63aad06da24d707c9e423503cad2dbb445 |
|
02-Aug-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: add cs_get_next_fence winsys callback
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| c5ff0d3e65d499dcb466c151ed48cdf67e43cdbb |
|
29-Jul-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: move radeon_winsys::cs_memory_below_limit to drivers
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 076db67217741aa820feadccc66067516d4cf4ca |
|
29-Jul-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: inline radeon_winsys::query_memory_usage
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 9646ae77992f895b481984c9f8861cc64501a4eb |
|
29-Jul-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon/winsyses: expose per-IB used_vram and used_gart to drivers
The following patches will use this.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 1a1cc67edd4c1ae08b739adaf78e014b828908de |
|
15-Jul-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: remove RADEON_FLUSH_KEEP_TILING_FLAGS flag
always set
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| a7d84f7731b2095ed5dc4f741213fef60a55dcd3 |
|
13-Jul-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: add a return value to cs_flush
Required by our UVD code.
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| ed3912d0daae717d70af9c595f1c36d817d9ceec |
|
08-Jul-2016 |
Marek Olšák <marek.olsak@amd.com> |
radeonsi: just save buffer sizes instead of buffers while recording IBs
whole buffer objects are not needed
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 7000dfd5c36dcfcc493e149e5aa5b4124d814d8a |
|
30-Jun-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
gallium/radeon: add depth/stencil_adjusted output to surface computation
This fixes a rare bug with stencil texturing -- seen on Polaris and Tonga,
though it's basically a function of the memory configuration so could affect
other parts as well.
Fixes piglit "unaligned-blit * stencil downsample" and various
"fbo-depth-array *stencil*" tests.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 19f8d2a843dc4b3b40b5b85371007e8ecc83186d |
|
29-Jun-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
gallium/radeon/winsyses: remove unused stencil_offset
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 8a4ace4a47a07323997da5c2dbc865a32df52451 |
|
01-Jul-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: add and use radeon_info::max_alloc_size (v2)
v2: - squashed the patches
- use INT_MAX
- clamp max_const_buffer_size
- check the DRM version in radeon
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 28f85eab49b28905e99a24fcb7f155063e5482e4 |
|
29-Jun-2016 |
sonjiang <sonny.jiang@amd.com> |
radeon uvd add uvd fw version for amdgpu
Signed-off-by: sonjiang <sonny.jiang@amd.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 1c5a10497ab93495710989fe6c7dd1e776c51b05 |
|
21-Jun-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon/winsyses: boolean -> bool, TRUE -> true, FALSE -> false
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 789618e3b4619225f1e86d52f7b692bf6eb866eb |
|
08-Jun-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: add micro_tile_mode to radeon_surf
for easier access
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 00389100b63d03adf70892b721d1b2e8b8d5e48a |
|
03-Jun-2016 |
Marek Olšák <marek.olsak@amd.com> |
winsys/amdgpu: enable DCC for mipmapped textures
Also add dcc_fast_clear_size for clearing only the necessary subset
of DCC. For no AA, it's equal to the size of the whole DCC level.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| aa7fe7044328039903993dde6edb32b7953ae9b0 |
|
03-Jun-2016 |
Marek Olšák <marek.olsak@amd.com> |
radeonsi: add per-level dcc_enabled flags
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| d4d733e39de2fc75aaa17d95998abdf19219cb38 |
|
06-Jun-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: don't allocate DCC for non-renderable texture formats
R9G9B9E5 is the only uncompressed one hopefully.
This fixes incorrect rendering not discovered (due to a lack of tests)
until DCC mipmapping was enabled.
Cc: 11.1 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 89ba076de4c8cfa171365700e6a3b017d5e3eeff |
|
07-May-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
radeon/winsys: introduce radeon_winsys_cs_chunk
We will chain multiple chunks together and will keep pointers to the older
chunks to support IB dumping.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 46ad3561be0b820333a515941bfb220591402573 |
|
06-May-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
radeon/winsys: add cs_check_space
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 0558564200466878f1a86e7a192d085b551079c4 |
|
07-May-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
gallium/radeon: add radeon_emitted to check for non-trivial IBs
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 60946c0d60610b03bc297df17ec7a3cca1e5f6e8 |
|
30-Apr-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: add a heuristic for better (S)DMA performance
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 9d8c283f285b26e17efaa017587c50e76d749583 |
|
08-May-2016 |
Marek Olšák <marek.olsak@amd.com> |
winsys/amdgpu: move gart_page_size to struct radeon_winsys
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 5541e11b9a1a4aa3b785d5d426276f9eb4795b61 |
|
01-May-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: remove stencil_tile_split from metadata
this is a leftover from the days when depth-stencil buffers were
allocated by the DDX
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 20a77397fac5c208761217a4e90ffc7eeb5b9032 |
|
01-May-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: remove tile_mode_array_valid flags
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| ef45825708e653daa232a9542187b534470e738a |
|
26-Apr-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: add radeon_surf::macro_tile_index
for indexing cik_macrotile_mode_array
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 92f6af2c4a360c6e499ead0fdfbd57e63615e9bb |
|
22-Apr-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: drop support for LINEAR_GENERAL layout
Unused. All texture imports use LINEAR_ALIGNED regardless of what
the DDX does.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 562c4a17b7e4fb56c7db679233b4a48f8b80b0f2 |
|
23-Apr-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
winsys/radeon: remove use_reusable_pool parameter from buffer_create
All callers set this parameter to true.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 7997b5f005d4051e84bf64d6d1294f3da5076e5a |
|
08-Aug-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/amdgpu: Add support for const IB.
v2: Use the correct IB to update request (Bas Nieuwenhuizen)
v3: Add preamble IB. (Bas Nieuwenhuizen)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| f4b77c764a2469b20cfe49ec3ea3cca8e49dea92 |
|
08-Aug-2015 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: move ring_type into winsyses
Not used by drivers.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 5a4b74d1ba2c156766a7a5dbfef099c7db5d6694 |
|
11-Apr-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: relax requirements on VRAM placements on APUs
This makes Tonga with vramlimit=128 2x faster in Heaven.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 0ba0933f488cbb22ad1a221b0057ac9753130916 |
|
10-Apr-2016 |
Marek Olšák <marek.olsak@amd.com> |
winsys/amdgpu: add support for 64-bit buffer sizes
v2: fail in radeon_winsys_bo_create if size > 32 bits
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 42e442d888ce2d3dcb95350d17c298791f5d76cc |
|
04-Nov-2015 |
Sonny Jiang <sonny.jiang@amd.com> |
radeonsi: add support for Polaris (v2)
v2: Polaris chips should be defined after Stoney
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> (v1)
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> (v1)
Signed-off-by: Leo Liu <leo.liu@amd.com> (v2 diff)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v2 diff)
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 8140154ae92c6bd022e409790bb069966a857aed |
|
11-Mar-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: remove old CS tracing
Cons:
- it was only integrated in r600g
- it doesn't work with GPUVM
- it records buffer contents at the end of IBs instead of at the beginning,
so the replay isn't exact
- it lacks an IB parser and user-friendliness
A better solution is apitrace in combination with gallium/ddebug, which
has a complete IB parser and can pinpoint hanging CP packets.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 5aea0d691988af945e09e1d7cca28ca0759cc309 |
|
14-Jan-2016 |
Christian König <christian.koenig@amd.com> |
radeon/winsys: add layer support for BO export
Add layer support to export individual array layers.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 04bc082f6a8bfc3b3774bb102d3200317609432e |
|
12-Jan-2016 |
Christian König <christian.koenig@amd.com> |
radeon/winsys: add offset support for BO import/export
Add offset support to handle NV12 offsets as well.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 737b6ed13e8f813987b5566004f0f45e9c55f1e8 |
|
22-Feb-2016 |
Marek Olšák <marek.olsak@amd.com> |
winsys/amdgpu: get PCI info
This will be queried by the OpenCL stack using an interop call.
I have tested that the values match lspci.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| f4aa3256ef2965d558b646b32d5e59280db7021d |
|
24-Feb-2016 |
Marek Olšák <marek.olsak@amd.com> |
winsys/amdgpu: allow drivers to set/get opaque metadata
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| bd1feb28273e8d7047304e5a2a02ca3d71de5533 |
|
24-Feb-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: rename winsys buffer_get/set_tiling to buffer_get/set_metadata
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 6011d7cf2528a02f1737b25bc180c2076a076173 |
|
24-Feb-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: remove rcs parameter from radeon_winsys::buffer_set_tiling
This was needed for DRM < 2.12.0 where the kernel was rewriting tiling flags
in IBs.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 260ef9c9bec8695d5988a91443988516d39d0240 |
|
24-Feb-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: use a structure for passing tiling flags from/to winsys
and call it radeon_bo_metadata
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| a5e2a173ddd6766650afe779de08b4585f132c18 |
|
23-Feb-2016 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: drop support for DRM 2.12.0 (kernel < 3.2)
in order to make some winsys interface changes easier
This distros should use new DRM if they want to use new Mesa:
Distro kernel mesa eol
SLES 10 2.6.16 6.4.2 2016-07
SLED 11 3.0 9.0.3 2022-03
RHEL 5 2.6.18 6.5.1 2017-03
RHEL 6 2.6.32 10.4.3 2020-11
Debian 6 2.6.32 7.7.1 2016-02
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| c577f2843a0341be1091c0eec81704772e667786 |
|
30-Jan-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: remove radeon_info::r600_tiling_config
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 4f96846d9d96fcb84fb0fb1823b3f59c3c426253 |
|
30-Jan-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: get pipe_interleave_bytes AKA group_bytes from the winsys
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 276621da451ae93321de05bf63baaf20ee2f32ca |
|
30-Jan-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: set num_banks in the winsys
amdgpu doesn't have to set this, because radeonsi gets it from tile mode
arrays by default.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 1e864d73799cfbcb29c4f22722b908bc39643347 |
|
30-Jan-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: rename & reorder members of radeon_info
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 0d8e4f958f83e0b67f07030c661a30b4e7c19425 |
|
19-Jan-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: rename max_compute_units -> num_good_compute_units
radeon sets this correctly, but not amdgpu
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| e976860638c6fb9f69b9cf3a82acaba55c08e274 |
|
12-Jan-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
gallium/radeon: do not reallocate user memory buffers
The whole point of AMD_pinned_memory is that applications don't have to map
buffers via OpenGL - but they're still allowed to, so make sure we don't break
the link between buffer object and user memory unless explicitly instructed
to.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| cf811faeff1eaa1aef817ae45314cc3419c44222 |
|
07-Dec-2015 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: remove radeon_winsys_cs_handle
"radeon_winsys_cs_handle *cs_buf" is now equivalent to "pb_buffer *buf".
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 93eb4f9287576e346838e7b38fec9b42518605f6 |
|
26-Oct-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/amdgpu: remove the dcc_enable surface flag
dcc_size is sufficient and doesn't need a further comment in my opinion.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| afa357c3b01322df31034f84613a4d8401a9486e |
|
21-Oct-2015 |
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> |
radeonsi: Allocate buffers for DCC.
As the alignment requirements can be 32 KiB or more, also adding
an aligned buffer creation function.
DCC is disabled for textures that can be shared as sharing the
DCC buffers has not been implemented yet.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| bf0d0ce0d57dce5df8195942d2eda6389d341fea |
|
21-Aug-2015 |
Samuel Li <samuel.li@amd.com> |
radeonsi: add support for Stoney asics (v3)
v2 (agd): rebase on mesa master, split pci ids to
separate commit
v3 (agd): use carrizo for llvm processor name for
llvm 3.7 and older
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Samuel Li <samuel.li@amd.com>
Cc: mesa-stable@lists.freedesktop.org
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 6f48e2bee15c484c4a4685712c6ba1f379ef6853 |
|
27-Sep-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/amdgpu: add winsys function cs_get_buffer_list
For debugging.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 93641f43416b8b8be8944e9d1473369bfda7f302 |
|
27-Sep-2015 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: stop using "reloc" in a few places
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 2edb0606397d16fe88d7b488285df379aaae5893 |
|
26-Sep-2015 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: tell the winsys the exact resource binding types
Use the priority flags and expand them.
This information will be used for debugging.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 8a9ab86ca6d510763bfe8532071c5fcfd977e3c4 |
|
30-Aug-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: add a flag telling how gfx IBs should be padded
This is always false on amdgpu (set by calloc).
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 6924ecac77d1d041420c571de9d31cff1d30aecc |
|
22-Aug-2015 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: read_registers should return bool meaning success or failure
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 0654a9ca17c17fe140f70d126c878a0ce4736b76 |
|
13-Jul-2015 |
Leo Liu <leo.liu@amd.com> |
radeon/vce: disable VCE dual instance for harvest part
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 767ad50a10d01274b1d1a877add12b5552ba6984 |
|
29-Jul-2015 |
Alex Deucher <alexander.deucher@amd.com> |
radeonsi: add support for FIJI (v4)
v2: incorporate comments from Marek
v3: add missing fiji case in winsys init
use tonga raster config (double check this)
v4: rebase on harvest patch
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v3)
Reviewed-by: Christian König <christian.koenig@amd.com> (v3)
Reviewed-by: David Zhang <david1.zhang@amd.com> (v3)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| e7fc664b91a5d886c2709d05a498f6a1dfbaf136 |
|
16-Apr-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/amdgpu: add addrlib - texture addressing and alignment calculator
This is an internal project that Catalyst uses and now open source will do
too.
v2: squashed these commits in:
- winsys/amdgpu: fix warnings in addrlib
- winsys/amdgpu: set PIPE_CONFIG and NUM_BANKS in tiling_flags
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 2eb067db0febcd71b4182153155e3e43f215624c |
|
16-Apr-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/amdgpu: add a new winsys for the new kernel driver
v2: - lots of changes according to Emil Velikov's comments
- implemented radeon_winsys::read_registers
v3: - a lot of new work, many of them adapt to libdrm interface changes
Squashed patches:
winsys/amdgpu: implement radeon_winsys context support
winsys/amdgpu: add reference counting for contexts
winsys/amdgpu: add userptr support
winsys/amdgpu: allocate IBs like normal buffers
winsys/amdgpu: add IBs to the buffer list, adapt to interface changes
winsys/amdgpu: don't use KMS handles as reloc hash keys
winsys/amdgpu: sync buffer accesses to different rings
winsys/amdgpu: use dependencies instead of waiting for last fence v2
gallium/radeon: unify buffer_wait and buffer_is_busy in the winsys interface (amdgpu part)
winsys/amdgpu: track fences per ring and be thread-safe
winsys/amdgpu: simplify waiting on a variable in amdgpu_fence_wait
gallium/radeon: allow the winsys to choose the IB size (amdgpu part)
winsys/amdgpu: switch to new amdgpu_cs_query_fence_status interface
winsys/amdgpu: handle fence and dependencies merge
winsys/amdgpu follow libdrm change to move user fence into UMD
winsys/amdgpu: use amdgpu_bo_va_op for va map/unmap v2
winsys/amdgpu: use the new tiling flags
winsys/amdgpu: switch to new GTT_USWC definition
winsys/amdgpu: expose amdgpu_cs_query_reset_state to drivers
winsys/amdgpu: fix valgrind warnings
winsys/amdgpu: don't use VRAM with APUs that don't have much of it
winsys/amdgpu: require LLVM 3.6.1 for VI because of bug fixes there
winsys/amdgpu: remove amdgpu_winsys::num_cpus
winsys/amdgpu: align BO size to page size
winsys/amdgpu: reduce BO cache timeout
winsys/amdgpu: remove useless flushing and waiting in amdgpu_bo_set_tiling
winsys/amdgpu: use amdgpu_device_handle as a unique device ID instead of fd
winsys/amdgpu: use safer access to amdgpu_fence_wait::signalled
winsys/amdgpu: allow maximum IB size of 4 MB
winsys/amdgpu: add ip_instance into amdgpu_fence
gallium/radeon: add RING_COMPUTE instead of RADEON_FLUSH_COMPUTE
winsys/amdgpu: set the ring type at CS initilization
winsys/amdgpu: query the GART page size from the kernel
winsys/amdgpu: correctly wait for shared buffers to become idle
winsys/amdgpu: set the amdgpu_cs_fence structure only once at fence creation
winsys/amdgpu: add a specific error message for cs_submit -> -ENOMEM
winsys/amdgpu: check num_active_ioctls before calling amdgpu_bo_wait_for_idle
winsys/amdgpu: clear user fence BO after allocating it
winsys/amdgpu: fix user fences
winsys/amdgpu: make amdgpu_winsys_create public
winsys/amdgpu: remove thread offloading
winsys/amdgpu: flatten the amdgpu_cs_context structure and simplify more
v4: require libdrm 2.4.63
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|
| 42d9f6323a523d786fc3797587fdf63048becceb |
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30-Apr-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: add an interface for contexts
Same idea as in libdrm_amdgpu.
A command stream can only be created for a specific context and it's always
submitted to that context.
This will mainly be used by amdgpu and it's required by the GPU reset status
query too.
(radeon only has a basic version of the query and thus doesn't need this)
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
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| 592ce6e2d1b2c804a95cb00c06e7bbb9d83f554b |
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06-Aug-2015 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: unify buffer_wait and buffer_is_busy in the winsys interface
The timeout parameter covers both cases.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
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| d587742650c262dea8007474b9956fd65472f8b2 |
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27-Jun-2015 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: allow the winsys to choose the IB size
Picked from the amdgpu branch.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
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| a2a1a5805fd617e7f3cc8be44dd79b50da07ebb9 |
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21-Jul-2015 |
Ilia Mirkin <imirkin@alum.mit.edu> |
gallium: replace INLINE with inline
Generated by running:
git grep -l INLINE src/gallium/ | xargs sed -i 's/\bINLINE\b/inline/g'
git grep -l INLINE src/mesa/state_tracker/ | xargs sed -i 's/\bINLINE\b/inline/g'
git checkout src/gallium/state_trackers/clover/Doxyfile
and manual edits to
src/gallium/include/pipe/p_compiler.h
src/gallium/README.portability
to remove mentions of the inline define.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
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| 914365c0eb039f66370cff166428c703e02ad510 |
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29-Apr-2015 |
Marek Olšák <marek.olsak@amd.com> |
r600g,radeonsi: implement get_device_reset_status
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
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| a582b22c6382f24d921e9fe8a24917100c1396f1 |
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16-Apr-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: add a private interface for radeon_surface
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
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| dcfbc006b6b07d41338b87c64cdc01c36608087b |
|
16-Apr-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: move radeon_winsys.h to drivers/radeon
/external/mesa3d/src/gallium/drivers/radeon/radeon_winsys.h
|