| 462e3cdf3b92464dab57da2b9e00986f8e6091be |
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03-Oct-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: make r600_gfx_write_fence more generic
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeonsi/si_perfcounter.c
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| 8c6ea5a6ffddd94cbdd5071d18b323f2e63b98c7 |
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02-Oct-2016 |
Marek Olšák <marek.olsak@amd.com> |
radeonsi: remove unnecessary #includes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
/external/mesa3d/src/gallium/drivers/radeonsi/si_perfcounter.c
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| fd9f54223dd8056bc4e9e17c53fe075e33a40f1f |
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30-Sep-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
gallium/radeon: emit relocations for query fences
This is only needed for r600 which doesn't have ARB_query_buffer_object and
therefore wouldn't really need the fences, but let's be optimistic about
filling in this feature gap eventually.
Cc: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeonsi/si_perfcounter.c
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| 8d45243e400d6d426a1aae735f8ccad608484584 |
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14-Sep-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
gallium/radeon: add r600_gfx_{write,wait}_fence
For bottom-of-pipe fences inside the gfx command stream.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeonsi/si_perfcounter.c
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| ad70c3954be0d04ca5c61d3e465ea7622916102f |
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15-Jul-2016 |
Marek Olšák <marek.olsak@amd.com> |
radeonsi: really wait for the second EOP event and not the first one
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeonsi/si_perfcounter.c
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| ad1782cfb5eaa633582c8a7d026690878ab54064 |
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04-May-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
radeonsi: expose performance counters as 64 bit
This is useful for shader-related counters, since they tend to quickly
exceed 32 bits.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeonsi/si_perfcounter.c
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| 28c2573b4f1b311145b3f21a1794adb3dcd5f61a |
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17-Apr-2016 |
Marek Olšák <marek.olsak@amd.com> |
radeonsi: don't flush CB/DB caches for performance counters
I'm not sure about this. This will make the engines go idle, but the caches
will be unflushed. This should match app behavior without performance
counters, which can be a good thing.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/drivers/radeonsi/si_perfcounter.c
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| 156e81f305b19f62b4d6ea98bf44a951e89dc947 |
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11-Dec-2015 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
radeonsi: add placeholder MC and SRBM performance counter groups
Yet another change motivated by AMD GPUPerfStudio compatibility. These groups
are not directly accessible from userspace, and AMD GPUPerfStudio does not
actually query them - it just requires them to be there. Hence, adding
a placeholder for now.
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeonsi/si_perfcounter.c
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| 988f4b31f3011327b389da2b5e0bd34e222bae86 |
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11-Dec-2015 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
radeonsi: re-order the SQ_xx performance counter blocks
This is yet another change motivated by appeasing AMD GPUPerfStudio's
hardcoding of performance counter group numbers.
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeonsi/si_perfcounter.c
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| 75affd73b085a681509fad7f0558be171cc2e5a4 |
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11-Dec-2015 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
radeonsi: re-order the perfcounter hardware blocks
As documented in the comment, AMD GPUPerfStudio unfortunately hardcodes the
order of performance counter groups. Let's do the pragmatic thing and present
the same order as Catalyst/Crimson.
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeonsi/si_perfcounter.c
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| c8d9d289ff6f08a5fb058971546585552683546d |
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13-Dec-2015 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
radeonsi: fix perfcounter selection for SI_PC_MULTI_BLOCK layouts
The incorrectly computed register count caused lockups.
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
/external/mesa3d/src/gallium/drivers/radeonsi/si_perfcounter.c
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| 80a16dece614ef3763e2817d10a45462367af8b2 |
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25-Nov-2015 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
radeon: delay the generation of driver query names until first use
This shaves a bit more time off the startup of programs that don't
actually use performance counters.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeonsi/si_perfcounter.c
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| ad22006892c5511dac7d0d680633a1b857da49fb |
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25-Nov-2015 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
radeonsi: implement AMD_performance_monitor for CIK+
Expose most of the performance counter groups that are exposed by Catalyst.
Ideally, the driver will work with GPUPerfStudio at some point, but we are not
quite there yet. In any case, this is the reason for grouping multiple
instances of hardware blocks in the way it is implemented.
The counters can also be shown using the Gallium HUD. If one is interested to
see how work is distributed across multiple shader engines, one can set the
environment variable RADEON_PC_SEPARATE_SE=1 to obtain finer-grained performance
counter groups.
Part of the implementation is in radeon because an implementation for
older hardware would largely follow along the same lines, but exposing
a different set of blocks which are programmed slightly differently.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/drivers/radeonsi/si_perfcounter.c
|