| 1a77e0c48d7762deba5227cf12f3ffda89ff1882 |
|
22-Dec-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer core] fix SIMD16 PackTraits pack() and unpack()
Fix routines for 8-bit and 16-bit formats used by optimized tile store.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
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| bd22c3d41151ce265e61d64f9034928f83d3c959 |
|
19-Dec-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer core] fix SIMD16 transpose functions
Fixed Transpose_16 methods of following formats:
Transpose8_8_8_8
Transpose8_8
Transpose32_32
Transpose16_16_16_16
Transpose16_16_16
Transpose16_16
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
|
| 937b7d8e5a97d1c3cc5ab7303c03dbdd2fdc8017 |
|
28-Oct-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer core] 16-wide tile store nearly completed
* All format combinations coded
* Fully emulated on AVX2 and AVX
* Known issue: the MSAA sample locations need to be adjusted for 8x2
Set ENABLE_AVX512_SIMD16 and USD_8x2_TILE_BACKEND to 1 in knobs.h to enable
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
|
| 78a0a09e48baaef6369fd9034ed693896195cf57 |
|
18-Oct-2016 |
George Kyriazis <george.kyriazis@intel.com> |
swr: [rasterizer core] Remove deprecated simd intrinsics
Used in abandoned all-or-nothing approach to converting to AVX512
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
|
| 488992221056edaf7111f9290afdf216c5e98d62 |
|
11-Oct-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer core/sim] 8x2 backend + 16-wide tile clear/load/store
Work in progress (disabled).
USE_8x2_TILE_BACKEND define in knobs.h enables AVX512 code paths
(emulated on non-AVX512 HW).
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
|
| 2966d9c691fd0cd51d83204cac6b3194b9dcb878 |
|
04-Oct-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer core] align Macrotile FIFO memory to SIMD size
Align and use streaming store instructions for BE fifo queues.
Provides slightly faster enqueue and doesn't pollute the caches.
Add appropriate memory fences to ensure streaming writes are
globally visible.
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
|
| 0f13a8f770ff27f2fbff2b2fc65752b5f4434d4a |
|
15-Jul-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer core] introduce simd16intrin.h
Refactoring to leave existing simd_* intrinsics in "simdintrin.h" unchanged,
adding corresponding simd16_* intrinsics in "simd16intrin.h" on the side,
with emulation, that we can use piecemeal, rather than the all-or-nothing
approach to bring up avx512.
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
|
| 1d09b3971aed8f86aa28e52b1dcec393ee5debc9 |
|
08-Jul-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer core] avx512 simd utility work
Enabling KNOB_SIMD_WIDTH = 16 for AVX512 pre-work and low level simd utils
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
|
| b6d2c9685154a6bed5c42d90af39213e9c274b59 |
|
01-Jun-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer] add support for building avx512 version
Currently, most code paths between AVX2 and AVX512 are identical
(see changes to knobs.h).
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
|
| db084f48ebb1d255fb73fe7e9728e7653fc39eaf |
|
30-Apr-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer] Miscellaneous backend changes
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
|
| ef293ee9c0034bce980c978e0e41a8ab2a9730d7 |
|
06-Apr-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer] Interpolation utility functions
v2: use _mm_cmpunord_ps for vIsNaN
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
|
| e1222ade0039289993fbec261408eea5e0d7d9ae |
|
14-Mar-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer] code styling and update copyrights
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
|
| 0c18900cfb65379dea11f699bafccdd50e5c87c0 |
|
09-Mar-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer common] add _simd_s[rl]lv_epi32
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
|
| aca55131843dec6da27f76308b2b4a145fc9e152 |
|
04-Mar-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer jitter] vpermps support
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
|
| abd4aa68cc1a7d8a20547069c617388eedb3673e |
|
24-Feb-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
swr: [rasterizer core] backend reorganization
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
|
| c6e67f5a9373e916a8d2333585cb5787aa5f7bb7 |
|
17-Feb-2016 |
Tim Rowley <timothy.o.rowley@intel.com> |
gallium/swr: add OpenSWR rasterizer
Acked-by: Roland Scheidegger <sroland@vmware.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/simdintrin.h
|