| 2b621c47aa515add6452a788c0c27067fc60be20 |
|
27-Dec-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: add new HUD query num-SDMA-IBs
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 6b8a371e00b715b630418ced2ee867e7b2f36b11 |
|
27-Dec-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: rename the num-ctx-flushes query to num-GFX-IBs
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 844f8268e1cde496a854a72e080558f3c5700583 |
|
04-Oct-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon/winsyses: set reasonable max_alloc_size
which is returned for GL_MAX_TEXTURE_BUFFER_SIZE.
It doesn't have any other use at the moment.
Bigger allocations are not rejected.
This fixes GL45-CTS.texture_buffer.texture_buffer_max_size on Bonaire.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 42ed8a6c9ccfb8b6b632c3be90fb03d292f53d25 |
|
02-Oct-2016 |
Matt Whitlock <freedesktop@mattwhitlock.name> |
gallium/winsys: replace calls to dup(2) with fcntl(F_DUPFD_CLOEXEC)
Without this fix, duplicated file descriptors leak into child processes.
See commit aaac913e901229d11a1894f6aaf646de6b1a542c for one instance
where the same fix was employed.
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Matt Whitlock <freedesktop@mattwhitlock.name>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| de84e99e454adede4f95c1cfd59f24c9dcc4e73d |
|
27-Sep-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
gallium/radeon/winsyses: add radeon_winsys::min_alloc_size
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| fb827c055cb1bdd2b18d0687c06c56b537d805f3 |
|
12-Sep-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
winsys/radeon: enable buffer allocation from slabs
Only enable for chips with GPUVM, because older driver paths do not take the
required offset into account.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| a1e391e39df2b1d8169e773a30153167ab8e13e8 |
|
12-Sep-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
winsys/radeon: add fine-grained fences for slab buffers
Note the logic for adding fences is somewhat different than for amdgpu,
because radeon has no scheduler and we therefore have no guarantee about
the order in which submissions from multiple threads are processed.
(Ironically, this is only an issue when "multi-threaded submission" is
disabled, because "multi-threaded submission" actually means that all
submissions happen from a single thread that happens to be separate from
the application's threads. If we only supported "multi-threaded
submission", the fence handling could be simplified by adding the fences
in that thread where everything is serialized.)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 339867c0774952e1174b8e3509383942e6e86b7f |
|
06-Sep-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
gallium/radeon/winsyses: remove #includes of pb_bufmgr.h
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 971ef7518fe06033222b53ea843792d3018c6ab2 |
|
18-Aug-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: add a driver query for AMDGPU_INFO_NUM_EVICTIONS
If the kernel driver doesn't support it, it returns 0.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 645d395d9af74573ed09223720e799073d34b647 |
|
05-Aug-2016 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: track the amount of mapped memory
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 8a4ace4a47a07323997da5c2dbc865a32df52451 |
|
01-Jul-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: add and use radeon_info::max_alloc_size (v2)
v2: - squashed the patches
- use INT_MAX
- clamp max_const_buffer_size
- check the DRM version in radeon
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 1c5a10497ab93495710989fe6c7dd1e776c51b05 |
|
21-Jun-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon/winsyses: boolean -> bool, TRUE -> true, FALSE -> false
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| bc4b7ebbfd1cab4a88f9349289dc7480b48b8291 |
|
22-Jun-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
winsys/radeon: add guard pages when R600_DEBUG=check_vm is enabled
This should help flush out GPU VM faults.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| cbb5adb90893a7c03f96f72f0665766a4007affd |
|
11-Jun-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/u_queue: allow the execute function to differ per job
so that independent types of jobs can use the same queue.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 2fba0aaa700bbdef37ac5da6da005b24be570e48 |
|
12-Jun-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/u_queue: add an option to name threads
for debugging
v2: correct the snprintf use
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 404d0d50d8aaf60597668e65a2d7c96cdea53aea |
|
11-Jun-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/u_queue: add an option to have multiple worker threads
independent jobs don't have to be stuck on only one thread
v2: use CALLOC & FREE
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| d8367e91f2e3d8426e77674b39f36c09ed9992ec |
|
12-Jun-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/u_queue: use a ring instead of a stack
and allow specifying its size in util_queue_init.
v2: use CALLOC & FREE
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| d794072b3e1f27b96aaf2c476fcd5dcc5fd9d445 |
|
11-Jun-2016 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: use the common job queue for multithreaded command submission v2
v2: fixup after renaming to util_queue_fence
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| bfa8a00920dc8ae8f2f6f4389f1dda8c950bff97 |
|
08-May-2016 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: use gart_page_size instead of private size_align
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 20a77397fac5c208761217a4e90ffc7eeb5b9032 |
|
01-May-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: remove tile_mode_array_valid flags
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| ed4fd542de73a03946f033a2150616423245b4e5 |
|
28-Apr-2016 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: drop support for kernels lacking tile mode array queries
This will allow us to simplify a lot of code around tiling.
Kernel 3.10 is required for SI support.
Kernel 3.13 is required for CIK support.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 5a4b74d1ba2c156766a7a5dbfef099c7db5d6694 |
|
11-Apr-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: relax requirements on VRAM placements on APUs
This makes Tonga with vramlimit=128 2x faster in Heaven.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| a5e2a173ddd6766650afe779de08b4585f132c18 |
|
23-Feb-2016 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: drop support for DRM 2.12.0 (kernel < 3.2)
in order to make some winsys interface changes easier
This distros should use new DRM if they want to use new Mesa:
Distro kernel mesa eol
SLES 10 2.6.16 6.4.2 2016-07
SLED 11 3.0 9.0.3 2022-03
RHEL 5 2.6.18 6.5.1 2017-03
RHEL 6 2.6.32 10.4.3 2020-11
Debian 6 2.6.32 7.7.1 2016-02
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 796ee76e2eeabbeed9ab41b012363cabd5497b33 |
|
10-Feb-2016 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: fix the num_tile_pipes comment to silence warnings
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 111602e15909ee2785334db008ac17d4eee8f391 |
|
10-Feb-2016 |
Alexandre Demers <alexandre.f.demers@gmail.com> |
winsys/radeon: better explain the num_tile_pipes fixup for TAHITI (v2)
v2: Clarify the relation between num_tiles_pipes and GB_TILE_MODE and the fix
needed for Tahiti as suggested by Marek.
Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 83b4d701c082bb43dc710be9ec423171ea11e8d1 |
|
07-Feb-2016 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: fix a wrong NUM_TILE_PIPES value from the kernel
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94019
Tested-by: Nick Sarnie <commendsarnex@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| c577f2843a0341be1091c0eec81704772e667786 |
|
30-Jan-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: remove radeon_info::r600_tiling_config
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 4f96846d9d96fcb84fb0fb1823b3f59c3c426253 |
|
30-Jan-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: get pipe_interleave_bytes AKA group_bytes from the winsys
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 276621da451ae93321de05bf63baaf20ee2f32ca |
|
30-Jan-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: set num_banks in the winsys
amdgpu doesn't have to set this, because radeonsi gets it from tile mode
arrays by default.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 294ec530c9829aead97487b1feb06361ef97cc2d |
|
30-Jan-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: just get num_tile_pipes from the winsys
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 1e864d73799cfbcb29c4f22722b908bc39643347 |
|
30-Jan-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: rename & reorder members of radeon_info
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| fb44cfadce97ad99cbca84880c628c8510055438 |
|
29-Jan-2016 |
Niels Ole Salscheider <niels_ole@salscheider-online.de> |
winsys/radeon: Do not deinit the pb cache if it was not initialized
This fixes a crash in pb_cache_release_all_buffers.
Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 0d8e4f958f83e0b67f07030c661a30b4e7c19425 |
|
19-Jan-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: rename max_compute_units -> num_good_compute_units
radeon sets this correctly, but not amdgpu
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| cf422d20ff9d9cc9ad9c015d878687803c311a4a |
|
06-Dec-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: use pb_cache instead of pb_cache_manager
This is a prerequisite for the removal of radeon_winsys_cs_handle.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| a450f96ba9b2fb33654bc529efab862fac765290 |
|
06-Dec-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: rename radeon_bomgr_init_functions
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 38ac20f7dd083f19e766f3d8a51e9b69c161e904 |
|
06-Dec-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: move variables from radeon_bomgr to radeon_drm_winsys
radeon_bomgr is going away.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 8a9ab86ca6d510763bfe8532071c5fcfd977e3c4 |
|
30-Aug-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: add a flag telling how gfx IBs should be padded
This is always false on amdgpu (set by calloc).
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 6924ecac77d1d041420c571de9d31cff1d30aecc |
|
22-Aug-2015 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: read_registers should return bool meaning success or failure
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| a83c36b5c0c64c717ced76db89bab900006648aa |
|
23-Aug-2015 |
Marek Olšák <marek.olsak@amd.com> |
Revert "radeon/winsys: increase the IB size for VM"
This reverts commit 567394112d904096abff1d994ab952f475dfb444.
It regressed performance. It looks like smaller IBs are better, because
the GPU goes idle quicker and there is less waiting for buffers and fences.
Cc: 11.0 <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 567394112d904096abff1d994ab952f475dfb444 |
|
31-Jul-2015 |
Marek Olšák <marek.olsak@amd.com> |
radeon/winsys: increase the IB size for VM
Luckily, there is a kernel query, so use the size from that.
It currently returns 256KB. It can be increased in the kernel.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 1307be519b8785249ee863a22115930299ff642a |
|
29-Jul-2015 |
Emil Velikov <emil.l.velikov@gmail.com> |
winsys/radeon: don't leak the fd when it is 0
Earlier commit added an extra dup(fd) to fix a ZaphodHeads issue.
Although it did not consider the (very unlikely) case where we might end
up with the valid fd == 0.
Fixes: 28dda47ae4d(winsys/radeon: Use dup fd as key in drm-winsys hash
table to fix ZaphodHeads.)
Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Mario Kleiner <mario.kleiner.de@gmail.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 28dda47ae4d974e3e032d60e8e0965c8c068c6d8 |
|
28-Jun-2015 |
Mario Kleiner <mario.kleiner.de@gmail.com> |
winsys/radeon: Use dup fd as key in drm-winsys hash table to fix ZaphodHeads.
Same problem and fix as for nouveau's ZaphodHeads trouble.
See patch ...
"nouveau: Use dup fd as key in drm-winsys hash table to fix ZaphodHeads."
... for reference.
Cc: "10.3 10.4 10.5 10.6" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 914365c0eb039f66370cff166428c703e02ad510 |
|
29-Apr-2015 |
Marek Olšák <marek.olsak@amd.com> |
r600g,radeonsi: implement get_device_reset_status
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 390f94e3581384838595185a06d5943089d3f9ab |
|
24-Jun-2015 |
Grigori Goronzy <greg@chown.ath.cx> |
winsys/radeon: reduce BO cache timeout
1000 ms is an extreme value for typical interactive loads. A large
cache has some disadvantages. Search for reusable BOs can take a long
time and memory might get exhausted.
Let's be rather conservative and use half of the old value,
500ms. This is beneficial to some loads on my test system and there
are no regressions.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 7796e8889a9a2cc1b454dc32d8da3d756404339a |
|
21-May-2015 |
Michel Dänzer <michel.daenzer@amd.com> |
winsys/radeon: Unmap GPU VM address range when destroying BO
But only when doing so is safe according to the
RADEON_INFO_VA_UNMAP_WORKING kernel query.
This avoids kernel GPU VM address range conflicts when the BO has other
references than the GEM handle being closed, e.g. when the BO is shared.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90537
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90873
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| a582b22c6382f24d921e9fe8a24917100c1396f1 |
|
16-Apr-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: add a private interface for radeon_surface
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 6d05396b0047c74d740c53156eda1a8574403498 |
|
24-Feb-2015 |
Marek Olšák <marek.olsak@amd.com> |
r600g,radeonsi: add a driver query returning GPU load
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 0b8e73a6ae2a77d0e9a7810cca5b181ba5f0893e |
|
24-Feb-2015 |
Marek Olšák <marek.olsak@amd.com> |
r600g,radeonsi: add driver queries for GPU temperature and shader+memory clocks
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| c688988b0d68ffee2d8f1d64b0d402e23e8ce49e |
|
11-Feb-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: test the userptr ioctl to see if it's present
There is no other way to check for support.
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| ccc5b60b06269a5d847b7fe9ebe08dc61b4d2030 |
|
12-Jan-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: increase the size of buffer cache
This should fix this performance regression:
https://bugs.freedesktop.org/show_bug.cgi?id=88227
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 0e1c085f17fdd774ff6b060dd03422e74ea3e2cc |
|
06-Dec-2014 |
Tom Stellard <thomas.stellard@amd.com> |
winsys/radeon: Always report at least 1 compute unit
All uses of this require that the value be at least one, so it's
easier to report at least one than having to wrap all uses
in MAX2(max_compute_units, 1).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 67dcbcd92cb9877a04747d6cf7fef14c2b8af8b3 |
|
09-Sep-2014 |
Tom Stellard <thomas.stellard@amd.com> |
radeonsi: Program RASTER_CONFIG for harvested GPUs v5
Harvested GPUs have some of their render backends disabled, so
in order to prevent the hardware from trying to render things
with these disabled backends we need to correctly program
the PA_SC_RASTER_CONFIG register.
v2:
- Write RASTER_CONFIG for all SEs.
v3:
- Set GRBM_GFX_INDEX.INSTANCE_BROADCAST_WRITES bit.
- Set GRBM_GFX_INFEX.SH_BROADCAST_WRITES bit when done setting
PA_SC_RASTER_CONFIG.
- Get num_se and num_sh_per_se from kernel.
v4:
- Get correct value for num_se
- Remove loop for setting PA_SC_RASTER_CONFIG
- Only compute raster config when a backend has been disabled.
v5: Michel Dänzer
- Fix computation for chips with multiple SEs
https://bugs.freedesktop.org/show_bug.cgi?id=60879
CC: "10.4 10.3" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| f058c6bbd1674bbbe1e1ef5f6f14b95307ec6312 |
|
30-Oct-2014 |
Marek Olšák <marek.olsak@amd.com> |
r300g: remove enabled/disabled hyperz and AA compression messages
It's annoying with octave. Reported by Michael Burian.
Cc: 10.2 10.3 <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| c4db733facd01f8f7503dec662ff79d278b103c1 |
|
16-Oct-2014 |
Michel Dänzer <michel.daenzer@amd.com> |
winsys/radeon: Use a single buffer cache manager again
The trick is to generate a unique buffer usage value for each possible
combination of domains and flags, with only one bit set each for the
domains and flags. This ensures pb_check_usage() only returns TRUE when
the domains and flags the cached buffer was created for exactly match
the requested ones.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 3ede67a4c6d77892296ffc5568ddf3accaa1af99 |
|
08-Oct-2014 |
Michel Dänzer <michel.daenzer@amd.com> |
winsys/radeon: Use separate caching buffer manager for each set of flags
Otherwise the caching buffer manager may return a buffer which was created
with a different set of flags, which can cause trouble.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| b419c651fbbf3660d7b53623dfa2e5a4c9bd3b98 |
|
20-Aug-2014 |
Marek Olšák <marek.olsak@amd.com> |
gallium/pb_bufmgr_cache: limit the size of cache
This should make a machine which is running piglit more responsive at times.
e.g. streaming-texture-leak can easily eat 600 MB because of how fast it
creates new textures.
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 36771dc60fc3934b326eeff4aa6d3a4d438222eb |
|
04-Aug-2014 |
Andreas Boll <andreas.boll.dev@gmail.com> |
winsys/radeon: fix nop packet padding for hawaii
The initial firmware for hawaii does not support type3 nop packet.
Detect the new hawaii firmware with query RADEON_INFO_ACCEL_WORKING2.
If the returned value is 3, then the new firmware is used.
This patch uses type2 for the old firmware and type3 for the new firmware.
It fixes the cases when the old firmware is used and the user wants to
manually enable acceleration.
The two possible scenarios are:
- the kernel has no support for the new firmware.
- the kernel has support for the new firmware but only the old firmware
is available.
Additionaly this patch disables GPU acceleration on hawaii if the kernel
returns a value < 2. In this case the kernel hasn't the required fixes
for proper acceleration.
v2:
- Fix indentation
- Use private struct radeon_drm_winsys instead of public struct radeon_info
- Rename r600_accel_working2 to accel_working2
v3:
- Use type2 nop packet for returned value < 3
v4:
- Fail to initialize winsys for returned value < 2
Cc: mesa-stable@lists.freedesktop.org
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Jérôme Glisse <jglisse@redhat.com>
Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 0e229b8c5aa5eb758cbc9e1176001e0f4d985a6a |
|
06-Aug-2014 |
Marek Olšák <marek.olsak@amd.com> |
radeonsi: always prefer SWITCH_ON_EOP(0) on CIK
The code is rewritten to take known constraints into account, while always
using 0 by default.
This should improve performance for multi-SE parts in theory.
A debug option is also added for easier debugging. (If there are hangs,
use the option. If the hangs go away, you have found the problem.)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
v2: fix a typo, set max_se for evergreen GPUs according to the kernel driver
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 07c65b85eada8dd34019763b6e82ed4257a9b4a6 |
|
19-Jun-2014 |
Michel Dänzer <michel.daenzer@amd.com> |
r600g/radeonsi: Use write-combined CPU mappings of some BOs in GTT
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 37d43ebb28ce8be38f3d9b0805b8b14354ce786d |
|
13-Jun-2014 |
Michel Dänzer <michel.daenzer@amd.com> |
winsys/radeon: Use separate caching buffer managers for VRAM and GTT
Should reduce overhead because the caching buffer manager doesn't need to
consider buffers of the wrong type.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 81385f7596ab3c336fb16b00864893421462b3fb |
|
18-Jul-2014 |
Tom Stellard <thomas.stellard@amd.com> |
winsys/radeon: Query the kernel for the number of SEs and SHs per SE
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 03aab2af16778f3ab8130ec664fd6a6066ca869a |
|
13-Jun-2014 |
Bruno Jiménez <brunojimen@gmail.com> |
radeon/compute: Implement PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
v2:
Add RADEON_INFO_ACTIVE_CU_COUNT as a define, as suggested by
Tom Stellard
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| aad669b1e90491f7c3951016456e8a2660d91a85 |
|
01-May-2014 |
Samuel Li <samuel.li@amd.com> |
radeonsi: add support for Mullins asics.
v2: name defaults to kabini for older llvm
v3: fix llvm version check
Signed-off-by: Samuel Li <samuel.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 0a41054b7faa9df4e4b8802f646a7e078389eb89 |
|
18-Apr-2014 |
Tom Stellard <thomas.stellard@amd.com> |
radeon/compute: Implement PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
Igor Gnatenko:
v2: in define RADEON_INFO_MAX_SCLK use 0x1a instead of 0x19 (upstream changes)
Bruno Jiménez:
v3: Convert the frequency to MHz from kHz after getting it in
'do_winsys_init'
Signed-off-by: Igor Gnatenko <i.gnatenko.brain@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 6dd045ef4074d23ac659eadb2388b12542e3aab8 |
|
19-Apr-2014 |
Marek Olšák <marek.olsak@amd.com> |
r600g: disable async DMA on R700
Cc: 10.0 10.1 mesa-stable@lists.freedesktop.org
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 3b0b44f7def0acb4f7a7aef086c0bece321418a6 |
|
09-Apr-2014 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: fix a race condition in initialization of radeon_winsys::screen
Create the screen in the winsys while the mutex is locked.
This also results in a nice code cleanup!
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| ac330d4130cb005c75972da2a701b674413456ba |
|
09-Apr-2014 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: fix a race condition between winsys_create and winsys_destroy
This also hides the reference count from drivers.
v2: update the reference count while the mutex is locked in winsys_create
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 7c57b01564b987259ec3ce8ed24266290fa60e75 |
|
08-Apr-2014 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: fix a race condition between 2 calls to radeon_winsys_create
This fixes random crashes of: piglit/glx-multithread-shader-compile.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| b5ebfc33b8d44de9947ace7cbb7fde1625e6c97f |
|
08-Apr-2014 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: remove unused radeon_info variables, move backend_map
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 34564c875357a5d0a1f103f29949eafc2f8e1b35 |
|
04-Apr-2014 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: remove definitions already present in radeon_drm.h
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| fb5cf3490ebbc173211b6c04c869e3fb9f4dbecc |
|
12-Feb-2014 |
Marek Olšák <marek.olsak@amd.com> |
r600g,radeonsi: add a bunch of useful queries for the HUD
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| e4a5a9fd2fdd5b5ae8b85ac743a228f409a21a70 |
|
14-Feb-2014 |
Brian Paul <brianp@vmware.com> |
gallium/pipebuffer: change pb_cache_manager_create() size_factor to float
Requested by Marek.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "10.1" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 8af358d8bc9f7563cd76313b16d7b149197a4b2c |
|
08-Feb-2014 |
Thomas Hellstrom <thellstrom@vmware.com> |
gallium/pipebuffer: Add a cache buffer manager bypass mask
In some situations, it may be desirable to bypass the cache at buffer
creation but to insert the buffer in the cache at buffer destruction.
One such situation is where we already have a kernel representation of a
buffer that we want to use, but we also want to insert it in the cache when
it's freed up.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: "10.1" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| c9e9b1862b472b2671b8d3b339f9f7624a272073 |
|
08-Feb-2014 |
Thomas Hellstrom <thellstrom@vmware.com> |
pipebuffer, winsys: Add a size match parameter to the cached buffer manager
In some situations it's important to restrict the sizes of buffers that the
cached buffer manager is allowed to return
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Cc: "10.1" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| cbdd052577e798e0cd7b39eb75cfebee406f8410 |
|
08-Jul-2013 |
Christian König <christian.koenig@amd.com> |
radeon/winsys: add VCE support v4
v2: add fw version query
v3: add README.VCE
v4: avoid error msg when kernel doesn't support it
Signed-off-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| fd33a6bcd7f1271e80332379131e82e00fe10586 |
|
26-Apr-2013 |
José Fonseca <jfonseca@vmware.com> |
gallium: Use C11 thread abstractions.
Note that PIPE_ROUTINE now returns an int.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 346b6abab9d0ec2d3aec6efe5a4bb03803666c2f |
|
05-Jan-2014 |
Marek Olšák <marek.olsak@amd.com> |
radeonsi: calculate NUM_BANKS for DB correctly on CIK
NUM_BANKS is not constant on CIK.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| bf3c3611130112062470299c154df2610633683a |
|
27-Dec-2013 |
Marek Olšák <marek.olsak@amd.com> |
radeonsi: set correct pipe config for Hawaii in DB
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| f5778f152b250cb233f4bee021baae916e504afe |
|
24-Sep-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeonsi: add support for Hawaii asics (v2)
Update additional register fields.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 3d3a0b9b67982a96a4c4d87f78c21204f3a48776 |
|
11-Oct-2013 |
Christian König <christian.koenig@amd.com> |
winsys/radeon: make radeon_drm_winsys_create public
Otherwise OpenGL/VDPAU interop won't work as expected.
Signed-off-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 21a57f9040b1688e6501509c88c79c2d277c8b1e |
|
12-Oct-2013 |
Christian König <christian.koenig@amd.com> |
winsys/radeon: cleanup CS offloading
Using atomic function for ncs is superfluous since it is
protected by a mutex anyway. Also lock the mutex only once
while retrieving the next CS for submission.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 4871128e58402385dc6f920884273c003a1124e1 |
|
25-Sep-2013 |
Christian König <christian.koenig@amd.com> |
radeon/winsys: keep screen pointer in winsys v2
Only create one screen for each winsys instance.
This helps with buffer sharing and interop handling.
v2: rebased and some minor cleanup
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 01a0dbcb96f133737a7f71b21125a58684d883cc |
|
21-Sep-2013 |
Christian König <christian.koenig@amd.com> |
winsys/radeon: share winsys between different fd's
Share the winsys between different fd's if they point to the same device.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 0653c66ef40ac553f91b29bbda7f59f7ce6948fa |
|
21-Sep-2013 |
Christian König <christian.koenig@amd.com> |
winsys/radeon: remove cs_queue_empty
Waiting for an empty queue is nonsense and can lead to deadlocks if we have
multiple waiters or another thread that continuously sends down new commands.
Just post the cs to the queue and immediately wait for it to finish.
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| f7ccb84aa1cd64703308dece03da0d4eb3bf4951 |
|
21-Sep-2013 |
Christian König <christian.koenig@amd.com> |
winsys/radeon: fix killing the CS thread
Kill the thread only after we checked that it's not used any more, not before.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| c88783047e2a0faa39d6f3ac6fbd3f26a480d5d3 |
|
09-Aug-2013 |
Alex Deucher <alexander.deucher@amd.com> |
r600g: disable GPUVM by default
Cayman and trinity systems still seem to suffer from
stability problems with GPUVM. This also fixes compute
on these asics. It can still be enabled for testing
by setting env var RADEON_VA=true.
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=65958
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
CC: "9.2" <mesa-stable@lists.freedesktop.org>
CC: "9.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| f29f206c93743d421c428383afaa2944f680d9c5 |
|
07-Jun-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeonsi: initial support for CIK chips
Add the infrastructure to differentiate them.
Just treat them like SI for now.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 5b3f1ea933a7ab6aa09ecdd1529b2baac558804e |
|
07-Jun-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeonsi: rename SI chip class from TAHITI to SI
Covers the entire family.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 761320b197ecc87221d070f5e961032ab0b665a4 |
|
07-Jun-2013 |
Alex Deucher <alexander.deucher@amd.com> |
winsys/radeon: add env var to disable VM on Cayman/Trinity
Set env var RADEON_VA=0 to disable VM on Cayman/Trinity.
Useful for debugging.
Note: this is a candidate for the 9.1 branch.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 4045c3d0601f1e3280625ed837846ecad5d051f7 |
|
13-May-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeonsi: add support for hainan chips
Note: this is a candidate for the 9.1 branch
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| abb96fdea70546f974ba59cbd00bc54afee9cfdb |
|
24-Apr-2013 |
Jerome Glisse <jglisse@redhat.com> |
winsys/radeon: consolidate tracing into winsys v2
This move the tracing timeout and printing into winsys and add
an debug environement variable for it (R600_DEBUG=trace_cs).
Lot of file touched because of winsys API changes.
v2: Do not write lockup file if ib uniq id does not match last one
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 817723baf8433fdcc9c71c165f9c6ea1d11bc4c4 |
|
10-Apr-2013 |
Marek Olšák <maraeo@gmail.com> |
winsys/radeon: use query_value for timestamp, remove query_timestamp
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 05fa3595e06c8b504f0eb86db8ed6ba88bffc98e |
|
05-Apr-2013 |
Marek Olšák <maraeo@gmail.com> |
r600g: add a query returning the amount of time spent during bo_map sync.
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| f91e4d2c9d714bb7d667956cd93f216c18a434f4 |
|
08-Apr-2013 |
Christian König <christian.koenig@amd.com> |
radeon/winsys: add uvd ring support to winsys v3
Separated from UVD patch for clarity.
v2: sync with next tree for 3.10
v3: as pointed out by Andreas Bool check for drm minor >= 32
http://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next-3.10-wip
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Andreas Boll <andreas.boll.dev@gmail.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 8ddae684aff5bae3f9bf12b35d938fe53aadc1a8 |
|
22-Mar-2013 |
Marek Olšák <maraeo@gmail.com> |
r600g: add a driver query returning the amount of requested VRAM and GTT memory
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 83e4407f443fb6baeccf9aefee291c82adcaa58b |
|
25-Jan-2013 |
Alex Deucher <alexander.deucher@amd.com> |
radeonsi: add support for Oland chips
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Note: this is a candidate for the 9.1 branch
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 6c064fd7492ea835f873112bc3189bb1920aad32 |
|
07-Jan-2013 |
Jerome Glisse <jglisse@redhat.com> |
radeon/winsys: add dma ring support to winsys v3
Add ring support, you can create a cs for each ring. DMA ring is
bit special regarding relocation as you must emit as much relocation
as there is use of the buffer.
v2: - Improved comment on relocation changes
- Use a single thread to queue cs submittion this simplify driver
code while not impacting performances. Rational for this is that
you have to wait for all previous submission to have completed
so there was never a case while we could have 2 different thread
submitting a command stream at the same time. This code just
consolidate submission into one single thread per winsys.
v3: - Do not use semaphore for empty queue signaling, instead use
cond var. This is because it's tricky to maintain an even number
of call to semaphore wait and semaphore signal (the number of
cs in the stack would for instance make that number vary).
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 3f584c211a0587c4cf5e6d36275390cd7181b5c8 |
|
11-Jan-2013 |
Marek Olšák <maraeo@gmail.com> |
r300g: random hyperz cleanups
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| ca474f98f2cda5cb333e9f851c7e0e31c9a6f823 |
|
04-Jan-2013 |
Jerome Glisse <jglisse@redhat.com> |
radeon/winsys: move radeon family/class identification to winsys
Upcoming async dma support rely on winsys knowing about GPU families.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 12dcbd5954676ee32604d82cacbf9a4259967e13 |
|
02-Dec-2012 |
Marek Olšák <maraeo@gmail.com> |
r300g: enable Hyper-Z by default on r500
I fixed the only known bugs on r500 with 0222b2bd4107b9e5cabfbc06c1a6ca3eae.
Now there are no piglit regressions with Hyper-Z and all apps I tested seem
to work.
To summarize how it works:
- Only one process can use it at a time. This is a hardware limitation.
- The first process to clear a zbuffer gets the exclusive access to use
Hyper-Z.
- Compositors don't use any zbuffer, so they won't steal it, but some web
browsers do, so make sure there's no web browser running if you want your
game to use Hyper-Z.
- There's no need to restart an app which couldn't get the access to Hyper-Z.
Just quit the app which took it, the driver can turn it on for the other app
in the middle of rendering.
- If an app gets the access to Hyper-Z, it prints "radeon: Acquired Hyper-Z"
to stdout.
r300-r400:
Hyper-Z will be enabled by default on r300-r400 once sufficient testing is
done with piglit and Lightsmark at least.
Be sure to set the env var RADEON_HYPERZ and run piglit with parameters: -c 0
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 73dd82061e7a5242c88b529c274784731462e039 |
|
30-Aug-2012 |
Christian König <deathsimple@vodafone.de> |
winsys/radeon: create only one winsys for each fd
Fixing problems with GLAMOR.
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 44f14ebd7b9ba7186342039d2602fdd6ea5077f5 |
|
05-Jul-2012 |
Marek Olšák <maraeo@gmail.com> |
r600g: implement timestamp query and get_timestamp hook
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 2f14202f52c9f61f5bb5bfb6beaf954ef5c18de9 |
|
12-Aug-2012 |
Marek Olšák <maraeo@gmail.com> |
configure.ac: bump libdrm_radeon requirement to 2.6.38
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 6e7756db14c362ede6fdc97454267a32b8eab1d4 |
|
17-Jun-2012 |
Marek Olšák <maraeo@gmail.com> |
r600g: enable streamout by default on r7xx and DRM 2.17.0
Now that it's in Linus's tree.
Has anyone had a chance to test streamout on Cayman recently?
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 88a2e2388bfeee66cb6d873558431b0e0af7e316 |
|
16-May-2012 |
Michel Dänzer <michel.daenzer@amd.com> |
radeonsi: Initial tiling support.
Largely based on the corresponding Evergreen support in r600g.
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| d0f6274489d4e4b9ce48cc377f502b0ccf64fae6 |
|
20-Mar-2012 |
Tom Stellard <thomas.stellard@amd.com> |
winsys/radeon: Get max_pipes from the kernel
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| a75c6163e605f35b14f26930dd9227e4f337ec9e |
|
06-Jan-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeonsi: initial WIP SI code
This commit adds initial support for acceleration
on SI chips. egltri is starting to work.
The SI/R600 llvm backend is currently included in mesa
but that may change in the future.
The plan is to write a single gallium driver and
use gallium to support X acceleration.
This commit contains patches from:
Tom Stellard <thomas.stellard@amd.com>
Michel Dänzer <michel.daenzer@amd.com>
Alex Deucher <alexander.deucher@amd.com>
Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The following commits were squashed in:
======================================================================
radeonsi: Remove unused winsys pointer
This was removed from r600g in commit:
commit 96d882939d612fcc8332f107befec470ed4359de
Author: Marek Olšák <maraeo@gmail.com>
Date: Fri Feb 17 01:49:49 2012 +0100
gallium: remove unused winsys pointers in pipe_screen and pipe_context
A winsys is already a private object of a driver.
======================================================================
radeonsi: Copy color clamping CAPs from r600
Not sure if the values of these CAPS are correct for radeonsi, but the
same changed were made to r600g in commit:
commit bc1c8369384b5e16547c5bf9728aa78f8dfd66cc
Author: Marek Olšák <maraeo@gmail.com>
Date: Mon Jan 23 03:11:17 2012 +0100
st/mesa: do vertex and fragment color clamping in shaders
For ARB_color_buffer_float. Most hardware can't do it and st/mesa is
the perfect place for a fallback.
The exceptions are:
- r500 (vertex clamp only)
- nv50 (both)
- nvc0 (both)
- softpipe (both)
We also have to take into account that r300 can do CLAMPED vertex colors only,
while r600 can do UNCLAMPED vertex colors only. The difference can be expressed
with the two new CAPs.
======================================================================
radeonsi: Remove PIPE_CAP_OUTPUT_READ
This CAP was dropped in commit:
commit 04e324008759282728a95a1394bac2c4c2a1a3f9
Author: Marek Olšák <maraeo@gmail.com>
Date: Thu Feb 23 23:44:36 2012 +0100
gallium: remove PIPE_SHADER_CAP_OUTPUT_READ
r600g is the only driver which has made use of it. The reason the CAP was
added was to fix some piglit tests when the GLSL pass lower_output_reads
didn't exist.
However, not removing output reads breaks the fallback for glClampColorARB,
which assumes outputs are not readable. The fix would be non-trivial
and my personal preference is to remove the CAP, considering that reading
outputs is uncommon and that we can now use lower_output_reads to fix
the issue that the CAP was supposed to workaround in the first place.
======================================================================
radeonsi: Add missing parameters to rws->buffer_get_tiling() call
This was changed in commit:
commit c0c979eebc076b95cc8d18a013ce2968fe6311ad
Author: Jerome Glisse <jglisse@redhat.com>
Date: Mon Jan 30 17:22:13 2012 -0500
r600g: add support for common surface allocator for tiling v13
Tiled surface have all kind of alignment constraint that needs to
be met. Instead of having all this code duplicated btw ddx and
mesa use common code in libdrm_radeon this also ensure that both
ddx and mesa compute those alignment in the same way.
v2 fix evergreen
v3 fix compressed texture and workaround cube texture issue by
disabling 2D array mode for cubemap (need to check if r7xx and
newer are also affected by the issue)
v4 fix texture array
v5 fix evergreen and newer, split surface values computation from
mipmap tree generation so that we can get them directly from the
ddx
v6 final fix to evergreen tile split value
v7 fix mipmap offset to avoid to use random value, use color view
depth view to address different layer as hardware is doing some
magic rotation depending on the layer
v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on
evergreen, align bytes per pixel to a multiple of a dword
v9 fix handling of stencil on evergreen, half fix for compressed
texture
v10 fix evergreen compressed texture proper support for stencil
tile split. Fix stencil issue when array mode was clear by
the kernel, always program stencil bo. On evergreen depth
buffer bo need to be big enough to hold depth buffer + stencil
buffer as even with stencil disabled things get written there.
v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen,
old ddx overestimate those. Fix linear case when pitch*height < 64.
Fix r300g.
v12 Fix linear case when pitch*height < 64 for old path, adapt to
libdrm API change
v13 add libdrm check
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
======================================================================
radeonsi: Remove PIPE_TRANSFER_MAP_PERMANENTLY
This was removed in commit:
commit 62f44f670bb0162e89fd4786af877f8da9ff607c
Author: Marek Olšák <maraeo@gmail.com>
Date: Mon Mar 5 13:45:00 2012 +0100
Revert "gallium: add flag PIPE_TRANSFER_MAP_PERMANENTLY"
This reverts commit 0950086376b1c8b7fb89eda81ed7f2f06dee58bc.
It was decided to refactor the transfer API instead of adding workarounds
to address the performance issues.
======================================================================
radeonsi: Handle PIPE_VIDEO_CAP_PREFERED_FORMAT.
Reintroduced in commit 9d9afcb5bac2931d4b8e6d1aa571e941c5110c90.
======================================================================
radeonsi: nuke the fallback for vertex and fragment color clamping
Ported from r600g commit c2b800cf38b299c1ab1c53dc0e4ea00c7acef853.
======================================================================
radeonsi: don't expose transform_feedback2 without kernel support
Ported from r600g commit 15146fd1bcbb08e44a1cbb984440ee1a5de63d48.
======================================================================
radeonsi: Handle PIPE_CAP_GLSL_FEATURE_LEVEL.
Ported from r600g part of commit 171be755223d99f8cc5cc1bdaf8bd7b4caa04b4f.
======================================================================
radeonsi: set minimum point size to 1.0 for non-sprite non-aa points.
Ported from r600g commit f183cc9ce3ad1d043bdf8b38fd519e8f437714fc.
======================================================================
radeonsi: rework and consolidate stencilref state setting.
Ported from r600g commit a2361946e782b57f0c63587841ca41c0ea707070.
======================================================================
radeonsi: cleanup setting DB_SHADER_CONTROL.
Ported from r600g commit 3d061caaed13b646ff40754f8ebe73f3d4983c5b.
======================================================================
radeonsi: Get rid of register masks.
Ported from r600g commits
3d061caaed13b646ff40754f8ebe73f3d4983c5b..9344ab382a1765c1a7c2560e771485edf4954fe2.
======================================================================
radeonsi: get rid of r600_context_reg.
Ported from r600g commits
9344ab382a1765c1a7c2560e771485edf4954fe2..bed20f02a771f43e1c5092254705701c228cfa7f.
======================================================================
radeonsi: Fix regression from 'Get rid of register masks'.
======================================================================
radeonsi: optimize r600_resource_va.
Ported from r600g commit 669d8766ff3403938794eb80d7769347b6e52174.
======================================================================
radeonsi: remove u8,u16,u32,u64 types.
Ported from r600g commit 78293b99b23268e6698f1267aaf40647c17d95a5.
======================================================================
radeonsi: merge r600_context with r600_pipe_context.
Ported from r600g commit e4340c1908a6a3b09e1a15d5195f6da7d00494d0.
======================================================================
radeonsi: Miscellaneous context cleanups.
Ported from r600g commits
e4340c1908a6a3b09e1a15d5195f6da7d00494d0..621e0db71c5ddcb379171064a4f720c9cf01e888.
======================================================================
radeonsi: add a new simple API for state emission.
Ported from r600g commits
621e0db71c5ddcb379171064a4f720c9cf01e888..f661405637bba32c2cfbeecf6e2e56e414e9521e.
======================================================================
radeonsi: Also remove sbu_flags member of struct r600_reg.
Requires using sid.h instead of r600d.h for the new CP_COHER_CNTL definitions,
so some code needs to be disabled for now.
======================================================================
radeonsi: Miscellaneous simplifications.
Ported from r600g commits 38bf2763482b4f1b6d95cd51aecec75601d8b90f and
b0337b679ad4c2feae59215104cfa60b58a619d5.
======================================================================
radeonsi: Handle PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION.
Ported from commit 8b4f7b0672d663273310fffa9490ad996f5b914a.
======================================================================
radeonsi: Use a fake reloc to sleep for fences.
Ported from r600g commit 8cd03b933cf868ff867e2db4a0937005a02fd0e4.
======================================================================
radeonsi: adapt to get_query_result interface change.
Ported from r600g commit 4445e170bee23a3607ece0e010adef7058ac6a11.
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 393d741788fa82896d4b1c9fd02402a83053afcf |
|
27-Mar-2012 |
Marek Olšák <maraeo@gmail.com> |
r600g: enable transform feedback on everything that isn't r700
Use R700_STREAMOUT=1 if you wanna hack transform feedback on r700.
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 622b65d33bcc46a6b2cede6081b32a26a4ec7c7f |
|
24-Feb-2012 |
Marek Olšák <maraeo@gmail.com> |
r600g: check for R600_STREAMOUT env var in winsys
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| ff60bd80582176f42166b3df27df41fbbf429449 |
|
07-Feb-2012 |
Dave Airlie <airlied@redhat.com> |
radeon: only init surface manage on r600
r300 fails to init the manager and then fails to init.
Signed-off-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| c0c979eebc076b95cc8d18a013ce2968fe6311ad |
|
30-Jan-2012 |
Jerome Glisse <jglisse@redhat.com> |
r600g: add support for common surface allocator for tiling v13
Tiled surface have all kind of alignment constraint that needs to
be met. Instead of having all this code duplicated btw ddx and
mesa use common code in libdrm_radeon this also ensure that both
ddx and mesa compute those alignment in the same way.
v2 fix evergreen
v3 fix compressed texture and workaround cube texture issue by
disabling 2D array mode for cubemap (need to check if r7xx and
newer are also affected by the issue)
v4 fix texture array
v5 fix evergreen and newer, split surface values computation from
mipmap tree generation so that we can get them directly from the
ddx
v6 final fix to evergreen tile split value
v7 fix mipmap offset to avoid to use random value, use color view
depth view to address different layer as hardware is doing some
magic rotation depending on the layer
v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on
evergreen, align bytes per pixel to a multiple of a dword
v9 fix handling of stencil on evergreen, half fix for compressed
texture
v10 fix evergreen compressed texture proper support for stencil
tile split. Fix stencil issue when array mode was clear by
the kernel, always program stencil bo. On evergreen depth
buffer bo need to be big enough to hold depth buffer + stencil
buffer as even with stencil disabled things get written there.
v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen,
old ddx overestimate those. Fix linear case when pitch*height < 64.
Fix r300g.
v12 Fix linear case when pitch*height < 64 for old path, adapt to
libdrm API change
v13 add libdrm check
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| bb1f0cf3508630a9a93512c79badf8c493c46743 |
|
02-Dec-2011 |
Jerome Glisse <jglisse@redhat.com> |
r600g: add support for virtual address space on cayman v11
Virtual address space put the userspace in charge of their GPU
address space. It's up to userspace to bind bo into the virtual
address space. Command stream can them be executed using the
IB_VM chunck.
This patch add support for this configuration. It doesn't remove
the 64K ib size limit thought this limit can be extanded up to
1M for IB_VM chunk.
v2: fix rendering
v3: fix rendering when using index buffer
v4: make vm conditional on kernel support add basic va management
v5: catch the case when we already have va for a bo
v6: agd5f: update on top of ioctl changes
v7: agd5f: further ioctl updates
v8: indentation cleanup + fix non cayman
v9: rebase against lastest mesa + improvement from Marek & Michel
v10: fix cut/paste bug
v11: don't rely on updated radeon_drm.h
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| b82a2a848c2f614be6186f411bc366ebe2f189bc |
|
09-Jan-2012 |
Jerome Glisse <jglisse@redhat.com> |
radeon/winsys: fix get info ioctl error checking
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| bbc320a94def6178028a4c46012c737839e1cf61 |
|
06-Dec-2011 |
Jerome Glisse <jglisse@redhat.com> |
gallium/radeon: fix indentation
Indentation cleanup, to keep consistency.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 3da5196263fb2ae60483044cbd34c94270e2accd |
|
10-Nov-2011 |
Brian Paul <brianp@vmware.com> |
radeon: silence initializer warnings
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| efbccfeca071b052bb8da0a7f0277000869b2ea1 |
|
04-Aug-2011 |
Marek Olšák <maraeo@gmail.com> |
winsys/radeon: remove the device file descriptor from the interface
r600g doesn't need it anymore.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 1b542aca6e998e544a90ccff310f74b2811b8db0 |
|
04-Aug-2011 |
Marek Olšák <maraeo@gmail.com> |
r600g: move more DRM queries into winsys/radeon
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| fb8cf51eeb91413e761e0510d1f8c11b8cd0a7ac |
|
22-Jul-2011 |
Marek Olšák <maraeo@gmail.com> |
r600g: move some queries into winsys/radeon
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| ce12f826927cf2d3ac3fd70d893abfb07adc23db |
|
22-Jul-2011 |
Marek Olšák <maraeo@gmail.com> |
r600g: first step into winsys/radeon
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| ce9daf6f0bda857c9ee5d021cfb444db6376bfe7 |
|
22-Jul-2011 |
Marek Olšák <maraeo@gmail.com> |
winsys/radeon: add R300 infix to winsys feature names
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 28a336dc38c478b809544e7404c4d1fddd873333 |
|
22-Jul-2011 |
Marek Olšák <maraeo@gmail.com> |
winsys/radeon: simplify how value queries work
This drops the get_value query and adds a function query_info, which returns
all the values in one nice structure.
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| 42ba8d141fe07fcfa6f39623d8226919bf27be9f |
|
06-Jun-2011 |
Benjamin Franzke <benjaminfranzke@googlemail.com> |
r300g: Remove is_r3xx
Use r300_pci_ids.h instead.
Reviewed-by: Alex Deucher <alexdeucher@gmail.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| fdd37af3f76ea3ac32f21e9a9c41979a9b33cc5c |
|
07-May-2011 |
Marek Olšák <maraeo@gmail.com> |
r300g: dynamically ask for and release Hyper-Z access
We ask for Hyper-Z access when clearing a zbuffer.
We release it if no zbuffer clear has been done for 2 seconds.
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|
| d35aeff4bb0b03450b2c3c08bd7f84db5bf43283 |
|
18-Apr-2011 |
Marek Olšák <maraeo@gmail.com> |
r300g/winsys: rename r300->radeon and do a little cleanup
Renaming a few files, types, and functions.
Also make the winsys independent of r300g.
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
|