| 2b621c47aa515add6452a788c0c27067fc60be20 |
|
27-Dec-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: add new HUD query num-SDMA-IBs
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| 6b8a371e00b715b630418ced2ee867e7b2f36b11 |
|
27-Dec-2016 |
Marek Olšák <marek.olsak@amd.com> |
gallium/radeon: rename the num-ctx-flushes query to num-GFX-IBs
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| fb827c055cb1bdd2b18d0687c06c56b537d805f3 |
|
12-Sep-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
winsys/radeon: enable buffer allocation from slabs
Only enable for chips with GPUVM, because older driver paths do not take the
required offset into account.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| a1e391e39df2b1d8169e773a30153167ab8e13e8 |
|
12-Sep-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
winsys/radeon: add fine-grained fences for slab buffers
Note the logic for adding fences is somewhat different than for amdgpu,
because radeon has no scheduler and we therefore have no guarantee about
the order in which submissions from multiple threads are processed.
(Ironically, this is only an issue when "multi-threaded submission" is
disabled, because "multi-threaded submission" actually means that all
submissions happen from a single thread that happens to be separate from
the application's threads. If we only supported "multi-threaded
submission", the fence handling could be simplified by adding the fences
in that thread where everything is serialized.)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| 0edebde9a48ab609c636050208505885da363593 |
|
12-Sep-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
winsys/radeon: add slab buffer list
Introducing radeon_bo::hash will reduce collisions between "real" buffers
and buffers from slabs.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| 645d395d9af74573ed09223720e799073d34b647 |
|
05-Aug-2016 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: track the amount of mapped memory
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| bc4b7ebbfd1cab4a88f9349289dc7480b48b8291 |
|
22-Jun-2016 |
Nicolai Hähnle <nicolai.haehnle@amd.com> |
winsys/radeon: add guard pages when R600_DEBUG=check_vm is enabled
This should help flush out GPU VM faults.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| d794072b3e1f27b96aaf2c476fcd5dcc5fd9d445 |
|
11-Jun-2016 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: use the common job queue for multithreaded command submission v2
v2: fixup after renaming to util_queue_fence
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| bfa8a00920dc8ae8f2f6f4389f1dda8c950bff97 |
|
08-May-2016 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: use gart_page_size instead of private size_align
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| cf422d20ff9d9cc9ad9c015d878687803c311a4a |
|
06-Dec-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: use pb_cache instead of pb_cache_manager
This is a prerequisite for the removal of radeon_winsys_cs_handle.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| 38ac20f7dd083f19e766f3d8a51e9b69c161e904 |
|
06-Dec-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: move variables from radeon_bomgr to radeon_drm_winsys
radeon_bomgr is going away.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| a83c36b5c0c64c717ced76db89bab900006648aa |
|
23-Aug-2015 |
Marek Olšák <marek.olsak@amd.com> |
Revert "radeon/winsys: increase the IB size for VM"
This reverts commit 567394112d904096abff1d994ab952f475dfb444.
It regressed performance. It looks like smaller IBs are better, because
the GPU goes idle quicker and there is less waiting for buffers and fences.
Cc: 11.0 <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| 567394112d904096abff1d994ab952f475dfb444 |
|
31-Jul-2015 |
Marek Olšák <marek.olsak@amd.com> |
radeon/winsys: increase the IB size for VM
Luckily, there is a kernel query, so use the size from that.
It currently returns 256KB. It can be increased in the kernel.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| a2a1a5805fd617e7f3cc8be44dd79b50da07ebb9 |
|
21-Jul-2015 |
Ilia Mirkin <imirkin@alum.mit.edu> |
gallium: replace INLINE with inline
Generated by running:
git grep -l INLINE src/gallium/ | xargs sed -i 's/\bINLINE\b/inline/g'
git grep -l INLINE src/mesa/state_tracker/ | xargs sed -i 's/\bINLINE\b/inline/g'
git checkout src/gallium/state_trackers/clover/Doxyfile
and manual edits to
src/gallium/include/pipe/p_compiler.h
src/gallium/README.portability
to remove mentions of the inline define.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| 7796e8889a9a2cc1b454dc32d8da3d756404339a |
|
21-May-2015 |
Michel Dänzer <michel.daenzer@amd.com> |
winsys/radeon: Unmap GPU VM address range when destroying BO
But only when doing so is safe according to the
RADEON_INFO_VA_UNMAP_WORKING kernel query.
This avoids kernel GPU VM address range conflicts when the BO has other
references than the GEM handle being closed, e.g. when the BO is shared.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90537
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90873
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| a582b22c6382f24d921e9fe8a24917100c1396f1 |
|
16-Apr-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: add a private interface for radeon_surface
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| dcfbc006b6b07d41338b87c64cdc01c36608087b |
|
16-Apr-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: move radeon_winsys.h to drivers/radeon
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| c688988b0d68ffee2d8f1d64b0d402e23e8ce49e |
|
11-Feb-2015 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: test the userptr ioctl to see if it's present
There is no other way to check for support.
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| c4db733facd01f8f7503dec662ff79d278b103c1 |
|
16-Oct-2014 |
Michel Dänzer <michel.daenzer@amd.com> |
winsys/radeon: Use a single buffer cache manager again
The trick is to generate a unique buffer usage value for each possible
combination of domains and flags, with only one bit set each for the
domains and flags. This ensures pb_check_usage() only returns TRUE when
the domains and flags the cached buffer was created for exactly match
the requested ones.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| 3ede67a4c6d77892296ffc5568ddf3accaa1af99 |
|
08-Oct-2014 |
Michel Dänzer <michel.daenzer@amd.com> |
winsys/radeon: Use separate caching buffer manager for each set of flags
Otherwise the caching buffer manager may return a buffer which was created
with a different set of flags, which can cause trouble.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| 36771dc60fc3934b326eeff4aa6d3a4d438222eb |
|
04-Aug-2014 |
Andreas Boll <andreas.boll.dev@gmail.com> |
winsys/radeon: fix nop packet padding for hawaii
The initial firmware for hawaii does not support type3 nop packet.
Detect the new hawaii firmware with query RADEON_INFO_ACCEL_WORKING2.
If the returned value is 3, then the new firmware is used.
This patch uses type2 for the old firmware and type3 for the new firmware.
It fixes the cases when the old firmware is used and the user wants to
manually enable acceleration.
The two possible scenarios are:
- the kernel has no support for the new firmware.
- the kernel has support for the new firmware but only the old firmware
is available.
Additionaly this patch disables GPU acceleration on hawaii if the kernel
returns a value < 2. In this case the kernel hasn't the required fixes
for proper acceleration.
v2:
- Fix indentation
- Use private struct radeon_drm_winsys instead of public struct radeon_info
- Rename r600_accel_working2 to accel_working2
v3:
- Use type2 nop packet for returned value < 3
v4:
- Fail to initialize winsys for returned value < 2
Cc: mesa-stable@lists.freedesktop.org
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Jérôme Glisse <jglisse@redhat.com>
Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| 07c65b85eada8dd34019763b6e82ed4257a9b4a6 |
|
19-Jun-2014 |
Michel Dänzer <michel.daenzer@amd.com> |
r600g/radeonsi: Use write-combined CPU mappings of some BOs in GTT
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| 37d43ebb28ce8be38f3d9b0805b8b14354ce786d |
|
13-Jun-2014 |
Michel Dänzer <michel.daenzer@amd.com> |
winsys/radeon: Use separate caching buffer managers for VRAM and GTT
Should reduce overhead because the caching buffer manager doesn't need to
consider buffers of the wrong type.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| ac330d4130cb005c75972da2a701b674413456ba |
|
09-Apr-2014 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: fix a race condition between winsys_create and winsys_destroy
This also hides the reference count from drivers.
v2: update the reference count while the mutex is locked in winsys_create
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| b5ebfc33b8d44de9947ace7cbb7fde1625e6c97f |
|
08-Apr-2014 |
Marek Olšák <marek.olsak@amd.com> |
winsys/radeon: remove unused radeon_info variables, move backend_map
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| fb5cf3490ebbc173211b6c04c869e3fb9f4dbecc |
|
12-Feb-2014 |
Marek Olšák <marek.olsak@amd.com> |
r600g,radeonsi: add a bunch of useful queries for the HUD
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| 0653c66ef40ac553f91b29bbda7f59f7ce6948fa |
|
21-Sep-2013 |
Christian König <christian.koenig@amd.com> |
winsys/radeon: remove cs_queue_empty
Waiting for an empty queue is nonsense and can lead to deadlocks if we have
multiple waiters or another thread that continuously sends down new commands.
Just post the cs to the queue and immediately wait for it to finish.
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| 05fa3595e06c8b504f0eb86db8ed6ba88bffc98e |
|
05-Apr-2013 |
Marek Olšák <maraeo@gmail.com> |
r600g: add a query returning the amount of time spent during bo_map sync.
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| 8ddae684aff5bae3f9bf12b35d938fe53aadc1a8 |
|
22-Mar-2013 |
Marek Olšák <maraeo@gmail.com> |
r600g: add a driver query returning the amount of requested VRAM and GTT memory
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| 6c064fd7492ea835f873112bc3189bb1920aad32 |
|
07-Jan-2013 |
Jerome Glisse <jglisse@redhat.com> |
radeon/winsys: add dma ring support to winsys v3
Add ring support, you can create a cs for each ring. DMA ring is
bit special regarding relocation as you must emit as much relocation
as there is use of the buffer.
v2: - Improved comment on relocation changes
- Use a single thread to queue cs submittion this simplify driver
code while not impacting performances. Rational for this is that
you have to wait for all previous submission to have completed
so there was never a case while we could have 2 different thread
submitting a command stream at the same time. This code just
consolidate submission into one single thread per winsys.
v3: - Do not use semaphore for empty queue signaling, instead use
cond var. This is because it's tricky to maintain an even number
of call to semaphore wait and semaphore signal (the number of
cs in the stack would for instance make that number vary).
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| ca474f98f2cda5cb333e9f851c7e0e31c9a6f823 |
|
04-Jan-2013 |
Jerome Glisse <jglisse@redhat.com> |
radeon/winsys: move radeon family/class identification to winsys
Upcoming async dma support rely on winsys knowing about GPU families.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|
| a75c6163e605f35b14f26930dd9227e4f337ec9e |
|
06-Jan-2012 |
Tom Stellard <thomas.stellard@amd.com> |
radeonsi: initial WIP SI code
This commit adds initial support for acceleration
on SI chips. egltri is starting to work.
The SI/R600 llvm backend is currently included in mesa
but that may change in the future.
The plan is to write a single gallium driver and
use gallium to support X acceleration.
This commit contains patches from:
Tom Stellard <thomas.stellard@amd.com>
Michel Dänzer <michel.daenzer@amd.com>
Alex Deucher <alexander.deucher@amd.com>
Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The following commits were squashed in:
======================================================================
radeonsi: Remove unused winsys pointer
This was removed from r600g in commit:
commit 96d882939d612fcc8332f107befec470ed4359de
Author: Marek Olšák <maraeo@gmail.com>
Date: Fri Feb 17 01:49:49 2012 +0100
gallium: remove unused winsys pointers in pipe_screen and pipe_context
A winsys is already a private object of a driver.
======================================================================
radeonsi: Copy color clamping CAPs from r600
Not sure if the values of these CAPS are correct for radeonsi, but the
same changed were made to r600g in commit:
commit bc1c8369384b5e16547c5bf9728aa78f8dfd66cc
Author: Marek Olšák <maraeo@gmail.com>
Date: Mon Jan 23 03:11:17 2012 +0100
st/mesa: do vertex and fragment color clamping in shaders
For ARB_color_buffer_float. Most hardware can't do it and st/mesa is
the perfect place for a fallback.
The exceptions are:
- r500 (vertex clamp only)
- nv50 (both)
- nvc0 (both)
- softpipe (both)
We also have to take into account that r300 can do CLAMPED vertex colors only,
while r600 can do UNCLAMPED vertex colors only. The difference can be expressed
with the two new CAPs.
======================================================================
radeonsi: Remove PIPE_CAP_OUTPUT_READ
This CAP was dropped in commit:
commit 04e324008759282728a95a1394bac2c4c2a1a3f9
Author: Marek Olšák <maraeo@gmail.com>
Date: Thu Feb 23 23:44:36 2012 +0100
gallium: remove PIPE_SHADER_CAP_OUTPUT_READ
r600g is the only driver which has made use of it. The reason the CAP was
added was to fix some piglit tests when the GLSL pass lower_output_reads
didn't exist.
However, not removing output reads breaks the fallback for glClampColorARB,
which assumes outputs are not readable. The fix would be non-trivial
and my personal preference is to remove the CAP, considering that reading
outputs is uncommon and that we can now use lower_output_reads to fix
the issue that the CAP was supposed to workaround in the first place.
======================================================================
radeonsi: Add missing parameters to rws->buffer_get_tiling() call
This was changed in commit:
commit c0c979eebc076b95cc8d18a013ce2968fe6311ad
Author: Jerome Glisse <jglisse@redhat.com>
Date: Mon Jan 30 17:22:13 2012 -0500
r600g: add support for common surface allocator for tiling v13
Tiled surface have all kind of alignment constraint that needs to
be met. Instead of having all this code duplicated btw ddx and
mesa use common code in libdrm_radeon this also ensure that both
ddx and mesa compute those alignment in the same way.
v2 fix evergreen
v3 fix compressed texture and workaround cube texture issue by
disabling 2D array mode for cubemap (need to check if r7xx and
newer are also affected by the issue)
v4 fix texture array
v5 fix evergreen and newer, split surface values computation from
mipmap tree generation so that we can get them directly from the
ddx
v6 final fix to evergreen tile split value
v7 fix mipmap offset to avoid to use random value, use color view
depth view to address different layer as hardware is doing some
magic rotation depending on the layer
v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on
evergreen, align bytes per pixel to a multiple of a dword
v9 fix handling of stencil on evergreen, half fix for compressed
texture
v10 fix evergreen compressed texture proper support for stencil
tile split. Fix stencil issue when array mode was clear by
the kernel, always program stencil bo. On evergreen depth
buffer bo need to be big enough to hold depth buffer + stencil
buffer as even with stencil disabled things get written there.
v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen,
old ddx overestimate those. Fix linear case when pitch*height < 64.
Fix r300g.
v12 Fix linear case when pitch*height < 64 for old path, adapt to
libdrm API change
v13 add libdrm check
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
======================================================================
radeonsi: Remove PIPE_TRANSFER_MAP_PERMANENTLY
This was removed in commit:
commit 62f44f670bb0162e89fd4786af877f8da9ff607c
Author: Marek Olšák <maraeo@gmail.com>
Date: Mon Mar 5 13:45:00 2012 +0100
Revert "gallium: add flag PIPE_TRANSFER_MAP_PERMANENTLY"
This reverts commit 0950086376b1c8b7fb89eda81ed7f2f06dee58bc.
It was decided to refactor the transfer API instead of adding workarounds
to address the performance issues.
======================================================================
radeonsi: Handle PIPE_VIDEO_CAP_PREFERED_FORMAT.
Reintroduced in commit 9d9afcb5bac2931d4b8e6d1aa571e941c5110c90.
======================================================================
radeonsi: nuke the fallback for vertex and fragment color clamping
Ported from r600g commit c2b800cf38b299c1ab1c53dc0e4ea00c7acef853.
======================================================================
radeonsi: don't expose transform_feedback2 without kernel support
Ported from r600g commit 15146fd1bcbb08e44a1cbb984440ee1a5de63d48.
======================================================================
radeonsi: Handle PIPE_CAP_GLSL_FEATURE_LEVEL.
Ported from r600g part of commit 171be755223d99f8cc5cc1bdaf8bd7b4caa04b4f.
======================================================================
radeonsi: set minimum point size to 1.0 for non-sprite non-aa points.
Ported from r600g commit f183cc9ce3ad1d043bdf8b38fd519e8f437714fc.
======================================================================
radeonsi: rework and consolidate stencilref state setting.
Ported from r600g commit a2361946e782b57f0c63587841ca41c0ea707070.
======================================================================
radeonsi: cleanup setting DB_SHADER_CONTROL.
Ported from r600g commit 3d061caaed13b646ff40754f8ebe73f3d4983c5b.
======================================================================
radeonsi: Get rid of register masks.
Ported from r600g commits
3d061caaed13b646ff40754f8ebe73f3d4983c5b..9344ab382a1765c1a7c2560e771485edf4954fe2.
======================================================================
radeonsi: get rid of r600_context_reg.
Ported from r600g commits
9344ab382a1765c1a7c2560e771485edf4954fe2..bed20f02a771f43e1c5092254705701c228cfa7f.
======================================================================
radeonsi: Fix regression from 'Get rid of register masks'.
======================================================================
radeonsi: optimize r600_resource_va.
Ported from r600g commit 669d8766ff3403938794eb80d7769347b6e52174.
======================================================================
radeonsi: remove u8,u16,u32,u64 types.
Ported from r600g commit 78293b99b23268e6698f1267aaf40647c17d95a5.
======================================================================
radeonsi: merge r600_context with r600_pipe_context.
Ported from r600g commit e4340c1908a6a3b09e1a15d5195f6da7d00494d0.
======================================================================
radeonsi: Miscellaneous context cleanups.
Ported from r600g commits
e4340c1908a6a3b09e1a15d5195f6da7d00494d0..621e0db71c5ddcb379171064a4f720c9cf01e888.
======================================================================
radeonsi: add a new simple API for state emission.
Ported from r600g commits
621e0db71c5ddcb379171064a4f720c9cf01e888..f661405637bba32c2cfbeecf6e2e56e414e9521e.
======================================================================
radeonsi: Also remove sbu_flags member of struct r600_reg.
Requires using sid.h instead of r600d.h for the new CP_COHER_CNTL definitions,
so some code needs to be disabled for now.
======================================================================
radeonsi: Miscellaneous simplifications.
Ported from r600g commits 38bf2763482b4f1b6d95cd51aecec75601d8b90f and
b0337b679ad4c2feae59215104cfa60b58a619d5.
======================================================================
radeonsi: Handle PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION.
Ported from commit 8b4f7b0672d663273310fffa9490ad996f5b914a.
======================================================================
radeonsi: Use a fake reloc to sleep for fences.
Ported from r600g commit 8cd03b933cf868ff867e2db4a0937005a02fd0e4.
======================================================================
radeonsi: adapt to get_query_result interface change.
Ported from r600g commit 4445e170bee23a3607ece0e010adef7058ac6a11.
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
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| c0c979eebc076b95cc8d18a013ce2968fe6311ad |
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30-Jan-2012 |
Jerome Glisse <jglisse@redhat.com> |
r600g: add support for common surface allocator for tiling v13
Tiled surface have all kind of alignment constraint that needs to
be met. Instead of having all this code duplicated btw ddx and
mesa use common code in libdrm_radeon this also ensure that both
ddx and mesa compute those alignment in the same way.
v2 fix evergreen
v3 fix compressed texture and workaround cube texture issue by
disabling 2D array mode for cubemap (need to check if r7xx and
newer are also affected by the issue)
v4 fix texture array
v5 fix evergreen and newer, split surface values computation from
mipmap tree generation so that we can get them directly from the
ddx
v6 final fix to evergreen tile split value
v7 fix mipmap offset to avoid to use random value, use color view
depth view to address different layer as hardware is doing some
magic rotation depending on the layer
v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on
evergreen, align bytes per pixel to a multiple of a dword
v9 fix handling of stencil on evergreen, half fix for compressed
texture
v10 fix evergreen compressed texture proper support for stencil
tile split. Fix stencil issue when array mode was clear by
the kernel, always program stencil bo. On evergreen depth
buffer bo need to be big enough to hold depth buffer + stencil
buffer as even with stencil disabled things get written there.
v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen,
old ddx overestimate those. Fix linear case when pitch*height < 64.
Fix r300g.
v12 Fix linear case when pitch*height < 64 for old path, adapt to
libdrm API change
v13 add libdrm check
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
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| ce12f826927cf2d3ac3fd70d893abfb07adc23db |
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22-Jul-2011 |
Marek Olšák <maraeo@gmail.com> |
r600g: first step into winsys/radeon
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
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| 28a336dc38c478b809544e7404c4d1fddd873333 |
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22-Jul-2011 |
Marek Olšák <maraeo@gmail.com> |
winsys/radeon: simplify how value queries work
This drops the get_value query and adds a function query_info, which returns
all the values in one nice structure.
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
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| fdd37af3f76ea3ac32f21e9a9c41979a9b33cc5c |
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07-May-2011 |
Marek Olšák <maraeo@gmail.com> |
r300g: dynamically ask for and release Hyper-Z access
We ask for Hyper-Z access when clearing a zbuffer.
We release it if no zbuffer clear has been done for 2 seconds.
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
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| d35aeff4bb0b03450b2c3c08bd7f84db5bf43283 |
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18-Apr-2011 |
Marek Olšák <maraeo@gmail.com> |
r300g/winsys: rename r300->radeon and do a little cleanup
Renaming a few files, types, and functions.
Also make the winsys independent of r300g.
/external/mesa3d/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
|