| 663fc64965fe1c6ae9994527b931b36230d622fc |
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11-Nov-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: rename brw_state_cache_check_size() to brw_program_cache_check_size()
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_compute.c
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| a85a8ecd32202b22e560bdf714b5715a168cc76e |
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09-Sep-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Eliminate brw->cs.prog_data pointer.
Just say no to:
- brw->cs.base.prog_data = &brw->cs.prog_data->base.base;
We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_cs_prog_data as needed.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_compute.c
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| 0e8f1eaf413d22e6860ccf4c93ccf256ad00aa6a |
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04-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: fix unused variable warning in brw_emit_gpgpu_walker()
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_compute.c
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| 94d0e7dc0848a5f70a550f2294e459eab51ace8f |
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22-Sep-2016 |
Lionel Landwerlin <lionel.g.landwerlin@intel.com> |
i965: get rid of duplicated values from gen_device_info
Now that we have gen_device_info mutable, we can update its values and drop
all copies we had in brw_context.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_compute.c
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| 9a939ebb47a0d37a6b29e3dbb1b20bdc9538a721 |
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16-Feb-2016 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/gen7: Use predicated rendering for indirect compute
On gen7 (Ivy Bridge, Haswell), we will get a GPU hang if an indirect
dispatch is used, but one of the dimensions is 0.
Therefore we use predicated rendering on the GPGPU_WALKER command to
handle this case.
Fixes piglit test: spec/arb_compute_shader/zero-dispatch-size
From the ARB_compute_shader spec, under DispatchCompute:
"If the work group count in any dimension is zero, no work groups are
dispatched."
And then for DispatchComputeIndirect:
... "is equivalent (assuming no errors are generated) to calling
DispatchCompute with <num_groups_x>, <num_groups_y> and
<num_groups_z>" ...
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94100
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_compute.c
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| 76732932ec3918bb9cc04ccd37bc1a8c37051683 |
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23-Nov-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Drop #include of main/glheader.h.
It's never used.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_compute.c
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| 63d7b33f516815ce3f9b3bb1b26a39f1545a4446 |
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24-Sep-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/cs: Setup surface binding for gl_NumWorkGroups
This will only be setup when the prog_data uses_num_work_groups
boolean is set.
At this point nothing will set uses_num_work_groups, but soon code
will set it when emitting code for the intrinsic that loads
gl_NumWorkGroups.
We can't emit this surface information earlier at the start of the
DispatchCompute* call because we may not have generated the program
yet. Until we generate the program, we don't know if the
gl_NumWorkGroups variable is accessed.
We also can't emit the surface as part of the brw_cs_state atom,
because we might not need the surface if gl_NumWorkGroups is not used
by the program.
Lastly, we cannot emit the surface later (after state upload) in the
DispatchCompute* call, because it needs to be run before the
brw_cs_state atom is emitted, since it changes the surface state.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_compute.c
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| d57a85f32b2242e19c2d20e91af0218d41e1e9fe |
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24-Sep-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/cs: Store compute invocation information in brw context
We will need this in an atom to setup a surface to read the
gl_NumWorkGroups values from.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_compute.c
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| ebbe6cdad7ab082d2b191fe6c7c0eaa6921d55de |
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18-Sep-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/cs: Implement DispatchComputeIndirect support
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_compute.c
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| 2310a65c28f809442c24fc8893c65ce7c7a4dca3 |
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16-Jun-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/compute: Fix undefined code with right_mask for SIMD32
Although we don't support SIMD32, krh pointed out that the left shift
by 32 is undefined by C/C++ for 32-bit integers.
Suggested-by: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_compute.c
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| 5328ffbe799bf40a971ebe804404ade91abddd33 |
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28-Aug-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/cs: Emit MEDIA_STATE_FLUSH after WALKER
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_compute.c
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| 8d87070af295140fb3558b6784dc6303fde11a67 |
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28-Aug-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/cs: Implement brw_emit_gpgpu_walker
Tested on Ivybridge, Haswell and Broadwell.
v2:
* Use SET_FIELD. (Ken)
* Use simd_size / 16 to support SIMD8/16/32. Ken suggested
that we might be able to do it arithmetically rather than just
supporting SIMD8 and SIMD16 with a conditional.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_compute.c
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| 013031b2291e87f2559a67c2c54b9004c71ef91b |
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10-Jan-2014 |
Paul Berry <stereotype441@gmail.com> |
i965: Implement DispatchCompute() back-end
brw_emit_gpgpu_walker will be implemented in a subsequent patch.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_compute.c
|