| 5189f0243a3dd8698c645bbe762b8a1a3caaf1a9 |
|
29-May-2016 |
Ilia Mirkin <imirkin@alum.mit.edu> |
mesa: hook up core bits of GL_ARB_shader_group_vote
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 9e5ce151a4708da60f9e5962cdefa5447a4dee04 |
|
27-Jan-2016 |
Iago Toral Quiroga <itoral@igalia.com> |
i965/fs: handle fp64 opcodes in brw_do_channel_expressions
In the case of the pack opcode we are already doing the
lowering in NIR, so no need to do it here. The unpack opcode
operates on scalars, so it should not be lowered.
In the case of frexp_sig and frexp_exp, they are lowered in
lower_instructions, so we don't have to care about them.
All the remaining opcodes involve conversions from and to doubles
and are business as usual.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 505a8fbdf8f2b6d2aaab5a04244cd3329f9dbe97 |
|
12-Apr-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Switch to NIR for ldexp lowering.
The old GLSL IR based lowering doesn't quite work right in all cases,
and fails several dEQP-GLES31 and Vulkan CTS tests. Jason's new
approach in NIR passes all the tests. There's not likely to be a ton
of advantage to lowering early in GLSL IR anyway, so...switch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 75c9def8ee44d3d134a2ddcb6418a6b3e3e4441c |
|
25-Jan-2016 |
Matt Turner <mattst88@gmail.com> |
i965/gen7+: Use NIR for lowering of pack/unpack opcodes.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 8709dc071323eb47be12f0929efe9e0741e9ef30 |
|
21-Jan-2016 |
Matt Turner <mattst88@gmail.com> |
glsl: Remove 2x16 half-precision pack/unpack opcodes.
i965/fs was the only consumer, and we're now doing the lowering in NIR.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 1a53a4fc7ab0a1f61504f62b9e1e9bce0bc86b52 |
|
22-Jan-2016 |
Matt Turner <mattst88@gmail.com> |
i965/fs: Switch from GLSL IR to NIR for un/packHalf2x16 scalarizing.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| eb63640c1d38a200a7b1540405051d3ff79d0d8a |
|
17-Jan-2016 |
Emil Velikov <emil.velikov@collabora.com> |
glsl: move to compiler/
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 24f984f64ae58c274f79eaf9148aea37df67131c |
|
18-Jan-2016 |
Emil Velikov <emil.velikov@collabora.com> |
nir: move glsl_types.{cpp,h} to compiler
Allows us to remove the SCons workaround :-)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| b85a229e1f542426b1c8000569d89cd4768b9339 |
|
08-Jan-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
glsl: Delete the ir_binop_bfm and ir_triop_bfi opcodes.
TGSI doesn't use these - it just translates ir_quadop_bitfield_insert
directly. NIR can handle ir_quadop_bitfield_insert as well.
These opcodes were only used for i965, and with Jason's recent patches,
we can do this lowering in NIR (which also gains us SPIR-V handling).
So there's not much point to retaining this GLSL IR lowering code.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 2268a50ffde18f9907ee7321c8b503b52a23fb05 |
|
30-Nov-2015 |
Matt Turner <mattst88@gmail.com> |
glsl: Remove ir_unop_any.
The GLSL IR to TGSI/Mesa IR paths for any_nequal have the same
optimizations the ir_unop_any paths had.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| f36993b46962eab4446bc1964eb47149751aee26 |
|
23-Nov-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Clean up #includes in the compiler.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| b9b40ef9b7644ea24768bc8b7464b1719efe99bf |
|
10-Oct-2015 |
Rob Clark <robclark@freedesktop.org> |
nir: remove dependency on glsl
Move glsl_types into NIR, now that the dependency on glsl_symbol_table
has been split out.
Possibly makes sense to rename things at this point, but if we do that
I'd like to keep it split out into a separate patch to make git history
easier to follow (IMHO).
v2: fix android build
v3: I f***ing hate scons.. but at least it builds
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 273f61a0051a794d1a39d70fb1dbf46a3ca3c63f |
|
13-Apr-2015 |
Samuel Iglesias Gonsalvez <siglesias@igalia.com> |
glsl: Add parser/compiler support for unsized array's length()
The unsized array length is computed with the following formula:
array.length() =
max((buffer_object_size - offset_of_array) / stride_of_array, 0)
Of these, only the buffer size needs to be provided by the backends, the
frontend already knows the values of the two other variables.
This patch identifies the cases where we need to get the length of an
unsized array, injecting ir_unop_ssbo_unsized_array_length expressions
that will be lowered (in a later patch) to inject the formula mentioned
above.
It also adds the ir_unop_get_buffer_size expression that drivers will
implement to provide the buffer length.
v2:
- Do not define a triop that will force backends to implement the
entire formula, they should only need to provide the buffer size
since the other values are known by the frontend (Curro).
v3:
- Call state->has_shader_storage_buffer_objects() in ast_function.cpp instead
of using state->ARB_shader_storage_buffer_object_enable (Tapani).
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 80511d176a49e754a18ce585bab413db7af63bf7 |
|
21-Jul-2015 |
Dave Airlie <airlied@redhat.com> |
i965: add support for ARB_shader_subroutine
This just adds some missing pieces to nir/i965,
it is lightly tested on my Haswell.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 5c71cf85315320fcb8b1cc2178f7f2d76b3beeef |
|
02-Apr-2015 |
Matt Turner <mattst88@gmail.com> |
glsl: Remove never used sin_reduced/cos_reduced.
These were added in commit f2616e56, presumably in preparation for
translating ARB vp/fp into GLSL IR. That never happened, and neither did
a lowering pass that actually generated these instructions.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| c8acbd1bfdafa892e6c5e9a6d9100aa2e69b9096 |
|
18-Mar-2015 |
Matt Turner <mattst88@gmail.com> |
glsl: Allow vector logic ops to be generated.
They're not accessible from the source language, but optimizations are
allowed to generate them.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 237dcb4aa7c39c59bfd225ae3d73caf709be216d |
|
05-Mar-2015 |
Mark Janes <mark.a.janes@intel.com> |
Fix invalid extern "C" around header inclusion.
System headers may contain C++ declarations, which cannot be given C
linkage. For this reason, include statements should never occur
inside extern "C".
This patch moves the C linkage statements to enclose only the
declarations within a single header.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| c442d0961e4ec6dcc304d652b637bb60687ce3cb |
|
14-Aug-2014 |
Dave Airlie <airlied@gmail.com> |
i965: just avoid warnings with fp64
This just fills in some blanks to avoid warnings in the i965 driver.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 4bfe8a1e613ac4798f52944e2ef1f34ebd859251 |
|
16-Jun-2014 |
Abdiel Janulgue <abdiel.janulgue@linux.intel.com> |
i965/fs: Add support for ir_unop_saturate
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| a39622452069b76f7562472cc15ddefd2db4b503 |
|
14-Aug-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965/fs: Support fine/coarse derivative opcodes
The quality level (fine/coarse/dont-care) is plumbed through to the
generator as a constant in src1.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 5ed147c26f800ffb11fb80b92aec9a772982aff6 |
|
17-Nov-2013 |
Chris Forbes <chrisf@ijw.co.nz> |
i965/fs: Skip channel expressions splitting for interpolation
The backend will have to do a message send, so we want to keep these in
one piece, just like texture ops.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 3d826729dabab53896cdbb1f453c76fab1c7e696 |
|
29-Jun-2014 |
Matt Turner <mattst88@gmail.com> |
i965: Use unreachable() instead of unconditional assert().
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| a76e5dce4fc8d50f8699c108833f24e80167d706 |
|
23-Dec-2013 |
Eric Anholt <eric@anholt.net> |
i965: Move compiler debugging output to stderr.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 61143b87c16231a2df0d69324d531503027f9aca |
|
17-Nov-2013 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Fix broken asserts
These would never fire.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| c4e6569fc838d712253e355f32ee40671a86579e |
|
18-Sep-2013 |
Matt Turner <mattst88@gmail.com> |
i965: Generate code for ir_binop_imul_high.
v2: Make accumulator's type match the type of the operation. Noticed by
Ken.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 014cce3dc49f5b0bfd7fbb1940ed661c9fc7bbd7 |
|
19-Sep-2013 |
Matt Turner <mattst88@gmail.com> |
i965: Generate code for ir_binop_carry and ir_binop_borrow.
Using the ADDC and SUBB instructions on Gen7.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| b2ab840130677bbe7b67de4727fcd91ee6506bb8 |
|
22-Aug-2013 |
Matt Turner <mattst88@gmail.com> |
glsl: Add support for ldexp.
v2: Drop frexp. Rebase on builtins rewrite.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 847726295861af4a34f0ec8eb7b3dfe9a6e178bd |
|
19-Aug-2013 |
Matt Turner <mattst88@gmail.com> |
i965: Add support for ir_triop_csel.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 530842127eabd41a809ee4d7136ff52857a4e685 |
|
24-Apr-2013 |
Matt Turner <mattst88@gmail.com> |
i965/fs: Add support for translating ir_triop_fma into MAD.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 01b79b2e3be506ca1fc5708fcfdb497d3ff19145 |
|
17-May-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add cases for ir_triop_vector_insert that assert.
brw_link_shader() unconditionally calls lower_vector_insert() with true
as the second parameter. This means that both constant and variable
indexed expressions will get lowered, so we should never see this in the
backend.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| e1e887679786cf3882e83b2a194f046b34a71f05 |
|
17-May-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add cases for ir_binop_vector_extract that assert.
do_vec_index_to_swizzle() should remove any vector extract operations
with a constant index. It's unconditionally called from
do_common_optimization().
do_vec_index_to_cond_assign() should remove the rest, and it is
unconditionally called from brw_link_shader(). This means that we
should never see ir_binop_vector_extract in the backend.
Silences compiler warnings.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 1f0f26d60c148e360908af34130c4e00dba8f3df |
|
10-Apr-2013 |
Matt Turner <mattst88@gmail.com> |
i965/fs: Add support for bit instructions.
Don't bother scalarizing ir_binop_bfm, since its results are
identical for all channels.
v2: Subtract result of FBH from 31 (unless an error) to convert
MSB counts to LSB counts.
v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref
channel_expressions) from appearing multiple times in the IR.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 0a1d145e5f1e6120e70e9b46e069167a0d653579 |
|
02-Dec-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Use the LRP instruction for ir_triop_lrp when possible.
v2 [mattst88]:
- Add BRW_OPCODE_LRP to list of CSE-able expressions.
- Fix op_var[] array size.
- Rename arguments to emit_lrp to (x, y, a) to clear confusion.
- Add LRP function to brw_fs.cpp/.h.
- Corrected comment about LRP instruction arguments in emit_lrp.
v3 [mattst88]:
- Duplicate MAD code for LRP instead of using a function pointer.
- Check for != GRF instead of == IMM in emit_lrp.
- Lower LRP on gen < 6.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
1
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 64dbc51b497fbd962f1b594c5613dcf56066f03b |
|
22-Jan-2013 |
Matt Turner <mattst88@gmail.com> |
i965: Assert that the 4x8 pack/unpack operations have been lowered
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 20dfa501b3950c1d2f5da7126091792f5eb67038 |
|
09-Jan-2013 |
Chad Versace <chad.versace@linux.intel.com> |
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4)
v2: Remove lewd comment. [for idr]
v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul]
- Improve comments. [for anholt, paul]
- Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack
methods. [for chadv]
v4: Factor our UD/W register conversion into helper function. [for anholt]
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2)
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 2ea3ab14f2182978f471674c9dfce029d37f70a7 |
|
10-Jul-2012 |
Eric Anholt <eric@anholt.net> |
glsl: Add a "ubo_load" expression type for fetches from UBOs.
Drivers will probably want to be able to take UBO references in a
shader like:
uniform ubo1 {
float a;
float b;
float c;
float d;
}
void main() {
gl_FragColor = vec4(a, b, c, d);
}
and generate a single aligned vec4 load out of the UBO. For intel,
this involves recognizing the shared offset of the aligned loads and
CSEing them out. Obviously that involves breaking things down to
loads from an offset from a particular UBO first. Thus, the driver
doesn't want to see
variable_ref(ir_variable("a")),
and even more so does it not want to see
array_ref(record_ref(variable_ref(ir_variable("a")),
"field1"), variable_ref(ir_variable("i"))).
where a.field1[i] is a row_major matrix.
Instead, we're going to make a lowering pass to break UBO references
down to expressions that are obvious to codegen, and amenable to
merging through CSE.
v2: Fix some partial thoughts in the ir_binop comment (review by Kenneth)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 11a7b93592c22c8165f8fde6395f76778fca452e |
|
14-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Add support for ir_unop_f2u to i965 backend.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 529476b5e4cd0591e0ec777b9bc2b5bec136822b |
|
07-Jun-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add forgotten bitcast operations in brw_fs_channel_expressions.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| 2f0edc60f4bd2ae5999a6afa656e3bb3f181bf0f |
|
26-Aug-2011 |
Chad Versace <chad@chad-versace.us> |
i965: Fix Android build by removing relative includes
Replace each occurence of
#include "../glsl/*.h"
with
#include "glsl/*.h"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
|
| b633ddeb9fd951ddc49e8a3fd25a946e5a16361f |
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14-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Implement new ir_unop_u2i and ir_unop_i2u opcodes.
No MOV is necessary since signed/unsigned integers share the same
bit-representation; it's simply a question of interpretation. In
particular, the fs_reg::imm union shouldn't need updating.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
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| d3073f58c17d8675a2ecdd5dfa83e5520c78e1a8 |
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21-Jan-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
Convert everything from the talloc API to the ralloc API.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
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| afb80c531530d0ff4c0efbc9f728f99a87165d8e |
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05-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix compile warning about missing opcodes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
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| 9935fe705df44bb633039ca74332cc0c126ccc30 |
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17-Nov-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
glsl: Remove the ir_binop_cross opcode.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
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| 33c4b2370f7546013e67e39ab9ec8ab2125e7597 |
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26-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Handle new ir_unop_round_even in channel expression splitting.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
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| 37758fb1cbb1ddcd106553763c1b1f222f4cfb47 |
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11-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Move FS backend structures to a header.
It's time to start splitting some of this up.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
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| bb70bd55596fa19f5775bac98bffb567f3ba1d9f |
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22-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Update expression splitting for the vector-result change to compares.
Fixes:
glsl1-precision exp2
glsl1-precision log2
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
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| d74bab1fb67fe1334fd80eaf0d4e224fc6d96f22 |
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22-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix the vector/expression splitting for the write_mask change.
+113 piglits.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
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| 6ef5f212343c0557c4fca272d8236226c1a7c87a |
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10-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add switch cases for ir_unop_noise, which should have been lowered.
Fixes compiler warnings.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
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| 3a8ad33dde2f059b82ebf09f5cffa66c86f2e734 |
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13-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add a pass for the FS to reduce vector expressions down to scalar.
This is a step towards implementing a GLSL IR backend for the 965
fragment shader. Because it has downsides with the current codegen,
it is hidden under the environment variable INTEL_NEW_FS.
This results in an increase in instruction count at the moment (1444
-> 1752 for glsl-fs-raytrace, 345 -> 359 on my demo), because dot
products are turned into a series of multiplies and adds instead of a
custom expansion of MULs and MACs, and by not splitting the variable
types up we don't get tree grafting and thus there are extra moves of
temporary storage. However, register count drops for the non-GLSL
path (64 -> 56 on my demo shader) because the register allocator sees
all the sub-operations.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
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