| 017c8df35b343de0bb23220d030089bf57fb28d4 |
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28-Sep-2016 |
Iago Toral Quiroga <itoral@igalia.com> |
i965/vec4: support multiple dispatch widths and groups in the IR builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_builder.h
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| d1f6f656973a2e18641441e3c97b30799a82de52 |
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27-Jun-2016 |
Matt Turner <mattst88@gmail.com> |
glsl: Separate overlapping sentinel nodes in exec_list.
I do appreciate the cleverness, but unfortunately it prevents a lot more
cleverness in the form of additional compiler optimizations brought on
by -fstrict-aliasing.
No difference in OglBatch7 (n=20).
Co-authored-by: Davin McCall <davmac@davmac.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_builder.h
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| 6e28976d35cf0a15c62bed1fd2ceeb734a3fc81e |
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07-Jul-2016 |
Samuel Iglesias Gonsálvez <siglesias@igalia.com> |
i965: enable the emission of the DIM instruction
v2 (Matt):
- Take a DF source argument for the DIM instruction emission
in the visitors.
- Indentation.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_builder.h
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| 0e9dc59a58e632979b3bdebb19d184bd22a0c182 |
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11-Feb-2016 |
Matt Turner <mattst88@gmail.com> |
i965: Make emit_minmax return an instruction*.
And use it in brw_fs_nir.cpp.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_builder.h
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| 2f2c00c7279e7c43e520e21de1781f8cec263e92 |
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11-Feb-2016 |
Matt Turner <mattst88@gmail.com> |
i965: Lower min/max after optimization on Gen4/5.
Gen4/5's SEL instruction cannot use conditional modifiers, so min/max
are implemented as CMP + SEL. Handling that after optimization lets us
CSE more.
On Ironlake:
total instructions in shared programs: 6426035 -> 6422753 (-0.05%)
instructions in affected programs: 326604 -> 323322 (-1.00%)
helped: 1411
total cycles in shared programs: 129184700 -> 129101586 (-0.06%)
cycles in affected programs: 18950290 -> 18867176 (-0.44%)
helped: 2419
HURT: 328
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_builder.h
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| 378d98f87e8048664309a66cb93ecf582e40d837 |
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11-Feb-2016 |
Matt Turner <mattst88@gmail.com> |
i965/vec4: Initialize force_writemask_all in vec4_builder().
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_builder.h
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| f9a9ba5eac2f1934bd7fecc92cd309f22411164b |
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02-Nov-2015 |
Matt Turner <mattst88@gmail.com> |
i965/vec4: Replace src_reg(imm) constructors with brw_imm_*().
Cuts 1.5k of .text.
Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_builder.h
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| b163aa01487ab5f9b22c48b7badc5d65999c4985 |
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27-Oct-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Rename GRF to VGRF.
The 2-bit hardware register file field is ARF, GRF, MRF, IMM.
Rename GRF to VGRF (virtual GRF) so that we can reuse the GRF name to
mean an assigned general purpose register.
Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_builder.h
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| 402cb7ce13da9319c96b585c1f39810a3719fae8 |
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24-Apr-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965/vec4: Introduce VEC4 IR builder.
See "i965/fs: Introduce FS IR builder." for the rationale.
v2: Drop scalarizing VEC4 builder.
v3: Take a backend_shader as constructor argument. Improve handling
of debug annotations and execution control flags. Rename "instr"
variable. Initialize cursor to NULL by default and add method to
explicitly point the builder at the end of the program.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_builder.h
|