| 45aee6be027805a6e51f2da7e9b7c954135f549d |
|
19-Nov-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete unused variable.
I forgot to delete this in 9ef2b9277d3bead6dbfa47e95794ca61e8be4e84.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 9ef2b9277d3bead6dbfa47e95794ca61e8be4e84 |
|
15-Nov-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Share URB configuration code between GL and Vulkan.
This code is far too complicated to cut and paste.
v2: Update the newly added genX_gpu_memcpy.c; const a few things.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 6d416bcd846a49414f210cd761789156c37a7b3e |
|
15-Nov-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use arrays in Gen7+ URB code.
So much of this code was cut and pasted per stage. We can accomplish
much of it by looping over shader stages.
Improves performance of OglBatch7 (version 6) by 1.50783% +/- 0.287049%
(n = 71) at 1024x768 on Cherryview.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 6656dd4b92f3f1d7984ead26dde1221e103e7392 |
|
15-Nov-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Drop brw->urb.{nr_*_entries,*_start} assignments from gen7_urb.c.
The context fields are for Gen4-5; setting them has always been useless.
There's no point in spending the cost in the hottest path in the driver.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 74d8612eedb67b3e39b6ba3b7d4d85d93a3153cd |
|
15-Nov-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Switch to roundf in HS/DS URB code.
Matt intentionally switched the VS calculation to be float-based in
commit c1da15709a0c0c2775bd9e534f67c60f7dc95ce8. Tessellation support
was written before this and rebased forward, and missed the change.
Now it's consistent.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| c87b5dee119da9696d9c1897dc7c96144b9ced7a |
|
15-Nov-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make URB code use prog_data for GS/tessellation enable checks.
If geometry/tessellation shaders are disabled, prog_data will be NULL
(see brw_state_upload.c). This consolidates dirty bits a little.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 639af2a7c637e39b2d30f9891f67da76af50cab7 |
|
15-Nov-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert devinfo->urb.min_*_entries into an array.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 58c09e72b15768524e5b76b55eae506391b663d8 |
|
15-Nov-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert devinfo->urb.max_*_entries into an array.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| ff366f3db4a117244c6076e5babd440c912200f9 |
|
09-Sep-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Eliminate brw->gs.prog_data pointer.
Just say no to:
- brw->gs.base.prog_data = &brw->gs.prog_data->base.base;
We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_gs_prog_data as needed.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| e512941537fbc25e97ecd778433e130769e2c6ec |
|
09-Sep-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Eliminate brw->tes.prog_data pointer.
Just say no to:
- brw->tes.base.prog_data = &brw->tes.prog_data->base.base;
We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_tes_prog_data as needed.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 82c97ac710e31bea1f954060950f8b9faf2fb4d6 |
|
09-Sep-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Eliminate brw->tcs.prog_data pointer.
Just say no to:
- brw->tcs.base.prog_data = &brw->tcs.prog_data->base.base;
We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_tcs_prog_data as needed.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 40258a13d5bf81303585eaf1859fcb85e373be3e |
|
09-Sep-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Eliminate brw->vs.prog_data pointer.
Just say no to:
- brw->vs.base.prog_data = &brw->vs.prog_data->base.base;
We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_vs_prog_data as needed.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arcero@collabora.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| eaf147cb463a2809366964ac4924e9aef719ffe7 |
|
03-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: rename max_ds_* variable to max_tes_*
Using consistent naming allows us to create macros more easily.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| b67633ce5e3ca29526f8378168ec312aa80c2861 |
|
03-Oct-2016 |
Timothy Arceri <timothy.arceri@collabora.com> |
i965: rename max_hs_* variables to max_tcs_*
Using consistent naming allows us to create macros more easily.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 94d0e7dc0848a5f70a550f2294e459eab51ace8f |
|
22-Sep-2016 |
Lionel Landwerlin <lionel.g.landwerlin@intel.com> |
i965: get rid of duplicated values from gen_device_info
Now that we have gen_device_info mutable, we can update its values and drop
all copies we had in brw_context.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| bc24590f0c579a2528fd94eb8d40dd4ce12eba29 |
|
22-Sep-2016 |
Lionel Landwerlin <lionel.g.landwerlin@intel.com> |
intel/i965: make gen_device_info mutable
Make gen_device_info a mutable structure so we can update the fields that
can be refined by querying the kernel (like subslices and EU numbers).
This patch does not make any functional change, it just makes
gen_get_device_info() fill a structure rather than returning a const
pointer.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 9694b23f66f4c41407289fb7d3ff25321042ef49 |
|
01-Dec-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename intelScreen to screen.
"intelScreen" is wordy and also doesn't fit our style guidelines.
"screen" is shorter, which is nice, because we use it fairly often.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 527f37199929932300acc1688d8160e1f3b1d753 |
|
23-Aug-2016 |
Jason Ekstrand <jason.ekstrand@intel.com> |
intel: s/brw_device_info/gen_device_info/
Generated by:
sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.c
sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.h
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.c
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.cpp
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.h
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 2a60654f568bc4a3808407a29b5c93007d921d44 |
|
23-May-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/urb: Allow blorp to record current settings
This makes it possible to skip urb re-configuration if the
subsequent renders agree with the settings.
Also allows blorp to allocate the maximun amount of vs entries
available. Core upload logic already knows how to calculate this.
Helps one synthetic benchmark.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 39fdee6b2df3cb297c0d2aba285f6991824867b9 |
|
18-May-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp/gen7+: Do not trigger push constant space reconfig
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 01c89ccc5d1529aa1efbae80c8ef641a59abbd93 |
|
23-Jun-2016 |
Ardinartsev Nikita <ardinar23@gmail.com> |
i965: Avoid division by zero.
Fixes regression introduced by af5ca43f2676bff7499f93277f908b681cb821d0
Cc: "12.0 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95419
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 9f37df06dafbf54cec6749543cac1baa77d0b5e2 |
|
09-Jun-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix issues with number of VS URB entries on Cherryview/Broxton.
Cherryview/Broxton annoyingly have a minimum number of VS URB entries
of 34, which is not a multiple of 8. When the VS size is less than 9,
the number of VS entries has to be a multiple of 8.
Notably, BLORP programmed the minimum number of VS URB entries (34), with
a size of 1 (less than 9), which is invalid.
It seemed like this could be a problem in the regular URB code as well,
so I went ahead and updated that to be safe.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 9c290b1e5468a66bd856ceee372079e3ce43def8 |
|
18-May-2016 |
Matt Turner <mattst88@gmail.com> |
Revert "i965/urb: fixes division by zero"
This reverts commit 2a8aa1e3deb99a1ae16d942318da648c1327ece5.
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 2a8aa1e3deb99a1ae16d942318da648c1327ece5 |
|
17-May-2016 |
Ardinartsev Nikita <ardinar23@gmail.com> |
i965/urb: fixes division by zero
Fixes regression introduced by af5ca43f2676bff7499f93277f908b681cb821d0
Reviewed-by: Matt Turner <mattst88@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95419
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 234b5f23f8047a837b8236e58301ad60fe63902b |
|
22-Apr-2016 |
Topi Pohjolainen <topi.pohjolainen@intel.com> |
i965/blorp: Use BRW_NEW_BLORP instead of trashing all state bits
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 6d5ce1b0433f4cbc5cd88b4bfeaf4cdcba6beda8 |
|
22-Apr-2016 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Make all atoms to track BRW_NEW_BLORP by default
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 9d35fecfb94e26a5fe6b361ebe83044fae9131bf |
|
18-Dec-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove unnecessary brw->tess_ctrl_program assertions.
This is trying to enforce the fact that the hardware requires HS, TE,
and DS to be enabled or disabled together. But it's kind of an ad-hoc
attempt, and not too useful.
More importantly, we aren't going to have a gl_shader_program for the
TCS which is automatically generated when none is present. (We'll just
handle it in the driver backend.) So, these will trip for no reason.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| f46dbfaed914e0e3463f3a28fc877695cd7e7834 |
|
18-Dec-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Consolidate BRW_NEW_TESS_{CTRL,EVAL}_PROGRAM flags.
For several reasons, I don't think it's particularly useful to have
separate flags:
1. Most of the time, tessellation shaders are paired, so both will be
replaced at the same time.
2. The data layout is tightly coupled. Both need to agree on the number
of per-patch slots in the VUE map. Even adding extra TCS outputs
that aren't read by the TES will trigger the need for recompiles.
3. The TCS is optional from an API perspective, but required by the
hardware whenever tessellation is enabled. So, atoms that deal with
the TCS must check brw->tess_eval_program (BRW_NEW_TESS_EVAL_PROGRAM?)
rather than brw->tess_ctrl_program to tell whether tessellation is
enabled.
So, not only is it unlikely to be useful, it's a bit confusing to get
right. Simply using one flag for both simplifies this.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| af5ca43f2676bff7499f93277f908b681cb821d0 |
|
09-Sep-2014 |
Chris Forbes <chrisf@ijw.co.nz> |
i965: Allocate URB space for HS and DS stages when required.
v2: (by Ken, incorporating feedback from Matt Turner):
- Rewrite the push constant allocation code to be clearer.
- Only apply the minimum VS entries workaround on Gen 8.
v3: (by Ken)
- Fix a bug in v2 where we failed to allocate the full push constant
space when the number of enabled stages didn't divide the available
push constant space evenly. (Any left over space is now allocated
to the PS, as it was in v1.)
- Fix an off-by-one error in v2's number of enabled stages calculation.
- Use DIV_ROUND_UP for nicer formatting.
- Line wrapping fixes.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 77cc2666b1935442f8a5b779c1d29977d029af01 |
|
01-Dec-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use DIV_ROUND_UP() in gen7_urb.c code.
This is a newer convention, which we prefer over ALIGN(x, n) / n.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 2405b75bc9c6b9fa9583e926bca313ed89911bc7 |
|
03-Sep-2015 |
Francisco Jerez <currojerez@riseup.net> |
i965: Define state flag to signal that the URB size has been altered.
This will make sure that we recalculate the URB layout anytime the URB
size is modified by the L3 partitioning code.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 27b1d344384ef89faf6d321bf4625d08ba6ff3bf |
|
18-Nov-2015 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix PIPE_CONTOL typo.
PIPE_CONTOL!!!
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| c1da15709a0c0c2775bd9e534f67c60f7dc95ce8 |
|
12-Jul-2015 |
Matt Turner <mattst88@gmail.com> |
i965: Use float calculations when double is unnecessary.
Literals without an f/F suffix are of type double, and implicit
conversion rules specify that the float in (float op double) be
converted to a double before the operation is performed. I believe float
execution was intended (in nearly all cases) or is sufficient (in the
case of gen7_urb.c).
Removes a lot of float <-> double conversion instructions and replaces
many double instructions with float instructions which are cheaper.
text data bss dec hex filename
4928659 195160 26192 5150011 4e953b i965_dri.so before
4928315 195152 26192 5149659 4e93db i965_dri.so after
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 4e56a9ad46ff7fe85308ce12e21719ff2b476516 |
|
20-Mar-2015 |
Jordan Justen <jordan.l.justen@intel.com> |
i965/state: Don't use brw->state.dirty.brw
Now, we only use ctx->NewDriverState.
I used this bash & sed command in the i965 directory:
for file in *.[ch] *.[ch]pp; do
sed -i -e 's/state\.dirty\.brw/ctx.NewDriverState/g' $file
done
Followed by manual changes to brw_state_upload.c.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 5f34a18f96e58aff1aca2d2971fca1c91dc6931d |
|
25-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete brw_state_flags::cache and related code.
It's been merged into brw_state_flags::brw for simplicity and
efficiency.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 4f24c168c87e9938f35f5ec135062408148be373 |
|
25-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move BRW_NEW_*_PROG_DATA flags to .brw (not .cache).
I put the BRW_NEW_*_PROG_DATA flags at the beginning so that
brw_state_cache.c can still continue using 1 << brw_cache_id.
I also added a comment explaining the difference between
BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM, as it took me a long time
to remember it.
Non-mechanical changes:
- brw_state_cache.c and brw_ff_gs.c now signal .brw, not .cache.
- brw_state_upload.c - INTEL_DEBUG=state changes.
- brw_context.h - bit definition merging.
v2: Correct the explanation of BRW_NEW_*_PROG_DATA to mention
state-based recompiles, and nix the "proper subset" claim,
as it's false. (Caught by Kristian Høgsberg).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| ce44b2061cf59264b4f22271e8d70cdc826af6de |
|
25-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename CACHE_NEW_*_PROG to BRW_NEW_*_PROG_DATA.
Now that we've moved a bunch of CACHE_NEW_* bits to BRW_NEW_*, the only
ones that are left are legitimately related to the program cache. Yet,
it seems a bit wasteful to have an entire bitfield for only 7 bits.
State upload is one of the hottest paths in the driver. For each atom
in the list, we call check_state() to see if it needs to be emitted.
Currently, this involves comparing three separate bitfields (mesa, brw,
and cache). Consolidating the brw and cache bitfields would save a
small amount of CPU overhead per atom. Broadwell, for example, has
57 state atoms, so this small savings can add up.
CACHE_NEW_*_PROG covers the brw_*_prog_data structures, as well as the
offset into the program cache BO (prog_offset). Since most uses refer
to brw_*_prog_data, I decided to use BRW_NEW_*_PROG_DATA as the name.
Removing "cache" completely is a bit painful, so I decided to do it in
several patches for easier review, and to separate mechanical changes
from manual ones. This one simply renames things, and was made via:
$ for file in *.[ch]; do
sed -i -e 's/CACHE_NEW_\([A-Z_\*]*\)_PROG/BRW_NEW_\1_PROG_DATA/g' \
-e 's/BRW_NEW_WM_PROG_DATA/BRW_NEW_FS_PROG_DATA/g' $file
done
Note that BRW_NEW_*_PROG_DATA is still in .cache, not .brw!
The next patch will remedy this flaw. It will also fix the
alphabetization issues.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| bea9b8e306e8424ffacbdfc99ca2fc91f1c9912b |
|
25-Nov-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Alphabetize brw_tracked_state flags and use a consistent style.
Most of the dirty flags were listed in some arbitrary order. Some used
bonus parenthesis. Some put multiple flags on one line, others put one
per line. Some used tabs instead of spaces...but only on some lines.
This patch settles on one flag per line, in alphabetical order, using
spaces instead of tabs, and sheds the unnecessary parentheses.
Sorting was mostly done with vim's visual block feature and !sort,
although I alphabetized short lists by hand; it was pretty manual.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 08599f668c5d991ab19376a19cb2e14e5245db95 |
|
07-May-2014 |
Eric Anholt <eric@anholt.net> |
i965: Skip recalculating URB allocations if the entry size didn't change.
We only get here if the VS/GS compiled programs change, but we can even
skip it if the VS/GS size didn't change.
Affects cairo runtime on glamor by -1.26471% +/- 0.674335% (n=234)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 864c463485aafaa2802b18a7427f8b75dc96e3ef |
|
03-Sep-2014 |
Jordan Justen <jordan.l.justen@intel.com> |
Revert 5 i965 patches: 8e27a4d2, 373143ed, c5bdf9be, 6f56e142, 88e3d404
Reverts
* "i965: Modify state upload to allow 2 different sets of state atoms."
8e27a4d2b3e4e74e9a77446bce49607433d86be3
* "i965: Modify dirty bit handling to support 2 pipelines."
373143ed9187c4d4ce1e3c486b5dd0880d18ec8b
* "i965: Create a macro for checking a dirty bit."
c5bdf9be1eca190417998d548fd140c1eca37a54
Conflicts:
src/mesa/drivers/dri/i965/brw_context.h
* "i965: Create a macro for setting all dirty bits."
6f56e1424d923fd80c84090fbf4506c9eaaffea1
Conflicts:
src/mesa/drivers/dri/i965/brw_blorp.cpp
src/mesa/drivers/dri/i965/brw_state_cache.c
src/mesa/drivers/dri/i965/brw_state_upload.c
* "i965: Create a macro for setting a dirty bit."
88e3d404dad009d8cff5124cf8acee7daeaceb64
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 88e3d404dad009d8cff5124cf8acee7daeaceb64 |
|
10-Jan-2014 |
Paul Berry <stereotype441@gmail.com> |
i965: Create a macro for setting a dirty bit.
This will make it easier to extend dirty bit handling to support
compute shaders.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 890287b96bfa2cae9bc3b477ab1eac2062f663ba |
|
25-Jun-2014 |
Greg Hunt <greg.hunt@mobica.com> |
i965: Remove unneeded VS workaround stalls on Baytrail.
According to the workarounds list, these stalls aren't needed on
production Baytrail systems. Piglit confirms that as well.
These cause a small slowdown when we are sending a large number of small
batches to the GPU. Removing these improves performance by up to 5% on
some CPU bound SynMark tests (Batch[4-7], DrvState1, HdrBloom,
Multithread, ShMapPcf).
Signed-off-by: Gregory Hunt <greg.hunt@mobica.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 9b1a6745f6b827170ac29a00510dbb740c81a116 |
|
25-Feb-2014 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Only emit VS state pipe control workaround on IVB and BYT.
According to the BSpec's 3D workarounds page, this is unnecessary on
shipping Haswell hardware, and was never necessary on Broadwell. It
unfortunately doesn't say anything about Baytrail.
The workaround database confirms those results for Ivybridge, Haswell,
and Broadwell. Baytrail is less clear - one page says it's necessary,
while the other says it isn't. For now, be conservative and leave it
enabled.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| a33d1339d5bfb32377be92957a493f0e3d84b31e |
|
04-Dec-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Double the push constant space multipliers on Broadwell too.
Broadwell has 2Kb push constant size increments like Haswell GT3.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| eadabec4cd0649af2827cce2bd71aea0cb6e7d06 |
|
09-Nov-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Disable workaround flush for push constants on Broadwell.
If it wasn't necessary for Haswell, it's likely not to be necessary for
Broadwell either.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 51c9cfc296318760aab421a79da727acd0e36311 |
|
18-Dec-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix 3DSTATE_PUSH_CONSTANT_ALLOC_PS packet creation.
When adding geometry shader support, we accidentally reversed the size
and offset parameters.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Cc: "10.0" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 7dfb4b2d00ddb8e5ee24d4c58eb9415dc4ccc21c |
|
05-Nov-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gen7: Emit workaround flush when changing GS enable state.
v2: Don't go to extra work to avoid extraneous flushes. (Previous
experiments in the kernel have suggested that flushing the pipeline
when it is already empty is extremely cheap).
Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 588ec545acc930470c605005292c8ef10adf4919 |
|
01-Sep-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gen7.5: Fix lower bound on number of VS URB entries.
Haswell GT2 and GT3 require the number of vertex shader URB entries to
be at least 64, not 32.
At the moment, we always meet this requirement automatically, because
in the absence of a geometry shader, we assign all available URB space
to the vertex shader. But when we turn on support for geometry
shaders, this lower limit will become important.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 555f9cf46d2108d1f9cdb52c112e5568f2a2ee2e |
|
18-Aug-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: Make sure constants re-sent after constant buffer reallocation.
The hardware requires that after constant buffers for a stage are
allocated using a 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,HS,DS,GS,PS}
command, and prior to execution of a 3DPRIMITIVE, the corresponding
stage's constant buffers must be reprogrammed using a
3DSTATE_CONSTANT_{VS,HS,DS,GS,PS} command.
Previously we didn't need to worry about this, because we only
programmed 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,HS,DS,GS,PS} once on
startup (or, previous to that, whenever BRW_NEW_CONTEXT was flagged).
But now that we reallocate the constant buffers whenever geometry
shaders are switched on and off, we need to make sure the constant
buffers are reprogrammed.
We do this by adding a new bit, BRW_NEW_PUSH_CONSTANT_ALLOCATION, to
brw->state.dirty.brw.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 27eecefc670c8b9e75f8520df7c9c7846923bf20 |
|
27-Mar-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gs: Allocate push constant space for use by GS.
Previously, we would always use the same push constant allocation
regardless of what shader programs were being run: the available push
constant space was split into 2 equal size partitions, one for the
vertex shader, and one for the fragment shader.
Now that we are adding geometry shader support, we need to do
something smarter. This patch adjusts things so that when a geometry
shader is in use, we split the available push constant space into 3
nearly-equal size partitions instead of 2.
Since the push constant allocation is now affected by GL state, it can
no longer be set up by brw_upload_initial_gpu_state(); instead it must
be set up by a state atom.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| df62421382c39678ac014e88cee7c73c64d42107 |
|
29-Aug-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gen7: Emit CS stall after 3DSTATE_PUSH_CONSTANT_ALLOC_PS.
This is required by the internal hardware docs and the PRM. Probably
the reason we were getting away with not doing it was because we only
emitted 3DSTATE_PUSH_CONSTANT_ALLOC_PS during startup. However that's
going to change with the introduction of geometry shaders.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| fffba41c6828b8f46a162185147d3e9b9cc479e4 |
|
27-Mar-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/gs: Allocate URB space for use by GS.
Previously, we gave all of the URB space (other than the small amount
that is used for push constants) to the vertex shader. However, when
a geometry shader is active, we need to divide it up between the
vertex and geometry shaders.
The size of the URB entries for the vertex and geometry shaders can
vary dramatically from one shader to the next. So it doesn't make
sense to simply split the available space in two. In particular:
- On Ivy Bridge GT1, this would not leave enough space for the worst
case geometry shader, which requires 64k of URB space.
- Due to hardware-imposed limits on the maximum number of URB entries,
sometimes a given shader stage will only be capable of using a small
amount of URB space. When this happens, it may make sense to
allocate substantially less than half of the available space to that
stage.
Our algorithm for dividing space between the two stages is to first
compute (a) the minimum amount of URB space that each stage needs in
order to function properly, and (b) the amount of additional URB space
that each stage "wants" (i.e. that it would be capable of making use
of). If the total amount of space available is not enough to satisfy
needs + wants, then each stage's "wants" amount is scaled back by the
same factor in order to fit.
When only a vertex shader is active, this algorithm produces
equivalent results to the old algorithm (if the vertex shader stage
can make use of all the available URB space, we assign all the space
to it; if it can't, we let it use as much as it can).
In the future, when we need to support tessellation control and
tessellation evaluation pipeline stages, it should be straightforward
to expand this algorithm to cover them.
v2: Use "unsigned" rather than "GLuint".
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 32e16e23377ecbba7783e33428ebb4575b874fe5 |
|
24-Aug-2013 |
Paul Berry <stereotype441@gmail.com> |
i965: rename legacy gs structs and functions to ff_gs.
"ff" is for "fixed function". This frees up the name "gs" to refer to
user-defined geometry shaders.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 7ce5c6b2147f9af524f4073b6ee3b29c0a5a1522 |
|
11-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Combine URB code emission into a single group.
All four URB packets need to be programmed together in order for the GPU
state to be valid. Putting them in separate BEGIN..ADVANCE blocks is
risky: if we're nearing the end of a batch, the batch could be flushed
inbetween two of the commands, causing the URB programming to be split
into two batchbuffers.
This -might- be okay with hardware contexts, but it offers no advantages
over keeping them together, and has a potential for hangs.
Putting them into a single BEGIN..ADVANCE block ensures they'll be kept
in the same batch, which seems wise.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 53631be4ebaa4fb13a7f129727c1cdd32fcc6f3d |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::gen and gt fields to brw_context.
Most functions no longer use intel_context, so this patch additionally
removes the local "intel" variables to avoid compiler warnings.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 794de2f3873bcedc78300b3ba69656adc755894c |
|
06-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move intel_context::is_<platform> flags to brw_context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| ca437579b3974b91a5298707c459908a628c1098 |
|
03-Jul-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Pass brw_context to functions rather than intel_context.
This makes brw_context available in every function that used
intel_context. This makes it possible to start migrating fields from
intel_context to brw_context.
Surprisingly, this actually removes some code, as functions that use
OUT_BATCH don't need to declare "intel"; they just use "brw."
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| fc800f0c60a21bc895d1db55a41fb99c306e1544 |
|
08-Jun-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Allocate push constant L3 space once at startup on Gen7+.
We always allocate the maximum amount of space and never change it, so
it makes sense to do it once. Programming it on startup also lets us
skip re-programming it from BLORP.
This removes a tiny amount of overhead from our drawing loop.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| eca2251f42f0234584d94268c29bddede3ff6451 |
|
24-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Update URB partitioning code for Haswell's GT3 variant.
Haswell's GT3 variant offers 32kB of URB space for push constants, while
GT1 and GT2 match Ivybridge, providing 16kB. Update the code to reserve
the full 32kB on GT3.
v2: Specify push constant size correctly. I thought GT3 reinterpreted
the value as multiples of 2kB, but it doesn't. You simply have to
program an even number.
NOTE: This is a candidate for stable branches.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 5fff3752c88255ea3f4eb26cddb2c996694b33b1 |
|
17-Feb-2013 |
Paul Berry <stereotype441@gmail.com> |
i965/vs: split brw_vs_prog_data into generic and VS-specific parts.
This will allow the generic parts to be re-used for geometry shaders.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
v2: Put urb_read_length and urb_entry_size in the generic struct.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 967514ce680f7bf785ab544c6174786dd20425de |
|
03-Apr-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use a variable for the push constant size in kB.
This clarifies that the offset of 2 is actually 16 kB / 8kB units.
It also keys both computations off of a single variable, which should
make it easier to change in the future.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 8cdb2d32ecd636a6d68840a68504c1fe1b14426b |
|
03-Apr-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Turn brw->urb.vs_size and gs_size into local variables.
These variables are only used within a single function, so we may as
well make them local variables.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| f7df7917e050b90df69c888e1f2ea0482ddd6b1d |
|
09-May-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/blorp: Allocate space for push constants on Gen7.
On Gen7, push constants for shader programs are stored in the URB, so
blorp code needs to set aside space for them. This was previously
unnecessary because blorp code was based on HiZ operations, which
don't require any shaders.
This patch adds a call from gen7_blorp_exec() to
gen7_allocate_push_constants(), to ensure that push constants are
assigned the correct location in the URB. It also extracts a new
function gen7_emit_urb_state() from gen7_upload_urb(), which is
re-used by gen7_blorp_emit_urb_config() to ensure that the URB regions
used by all the pipeline stages leave room for the push constants.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 709f50928e1d4df755ffb90ec9f33ba6c9605a32 |
|
19-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Emit Ivybridge VS workaround flushes.
I recently discovered this text in the BSpec. It seems wise to comply,
though I haven't observed it to fix anything yet.
Fixes a regression in glean/fbo since 28cfa1fa213fe.
NOTE: This is a candidate for stable release branches.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45221
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 28cfa1fa213fe7ba6e5b57e61da663a6c3bf0c13 |
|
11-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't reallocate push constant URB space on new VS programs.
The gen7_urb atom depends on CACHE_NEW_VS_PROG and CACHE_NEW_GS_PROG,
causing gen7_upload_urb() to be called when switching to a new VS
program.
In addition to partitioning the URB space between the VS and GS,
gen7_upload_urb() also allocated space for VS and PS push constants.
Unfortunately, this meant that whenever CACHE_NEW_VS was flagged, we'd
reallocate the space for the PS push constants. According to the BSpec,
after sending 3DSTATE_PUSH_CONSTANT_ALLOC_PS, we must reprogram
3DSTATE_CONSTANT_PS prior to the next 3DPRIMITIVE.
Since our URB allocation for push constants is entirely static, it makes
sense to split it out into its own atom that only subscribes to
BRW_NEW_CONTEXT. This avoids reallocating the space and trashing
constants.
Fixes a rendering artifact in Extreme Tuxracer, where instead of a snow
trail, you'd get a bright red streak (affectionately known as the
"bloody penguin bug").
This also explains why adding VS-related dirty bits to gen7_ps_state
made the problem disappear: it made 3DSTATE_CONSTANT_PS be emitted after
every 3DSTATE_PUSH_CONSTANT_ALLOC_PS packet.
NOTE: This is a candidate for the 7.11 branch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38868
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| ab8637b03fbf2594bd1ed9ea70982b166ef991be |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fold the gen6/7 URB state prepare()/emit() together.
No other unit cares about the prepare state, unlike gen4-5.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
|
| 5ddc518401ae69ad92218643f00ef50617a0f11d |
|
29-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/gen7: Add missing ! to brw->gs.prog_active assertion.
A typo in commit c173541d9769 accidentally removed the !.
It's supposed to assert that there is _not_ an active GS program.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38762
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
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| c173541d9769d41a85cc899bc49699a3587df4bf |
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27-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use state streaming on programs, and state base address on gen5+.
There will be a little bit of thrashing of the program cache BO as the
cache warms up, but once the application is in steady state, this
reduces relocations on gen5 and later.
On my T420 laptop, cairogl firefox-talos-gfx performance improves 2.6%
+/- 1.3% (n=6). No statistically significant performance difference
on nexuiz (n=5).
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
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| 8832920c298f4e13ffd5e53feeba509be69edb16 |
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27-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Initial Ivybridge URB space partitioning, including push constants.
Currently this always reserves 16kB for push constants, regardless of
how much space is needed, and partitions it evenly betwen the VS and FS.
This is probably not ideal, but is straightforward.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/gen7_urb.c
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