f4ba40fc419a9d484da9be1df051ad03327ce4f4 |
|
19-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Remove pool blocking and assembler enablement from the API The MacroAssemblerInsterface and AssemblerBase classes define methods that should not be used directly. Instead, scope utilities should be used. This patch hides the following methods from the user: ~~~ void MacroAssemblerInterface::SetAllowMacroInstructions(bool allow); void AssemblerBase::SetAllowAssembler(); void MacroAssemblerInterface::BlockPools(); void MacroAssemblerInterface::ReleasePools(); void MacroAssemblerInterface::EnsureEmitPoolsFor(size_t size); ~~~ Change-Id: I26b55c560cd94a2158757ca969c6bf95f7ba743b
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
f5d9808e6dd26daf325219d67a304173a1909f30 |
|
20-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Remove support for loading from a label using the MacroAssembler This patch removes the following API from the macro-assembler: ~~~ void Ldr(Condition cond, Register rt, Label* label); void Ldrb(Condition cond, Register rt, Label* label); void Ldrd(Condition cond, Register rt, Register rt2, Label* label); void Ldrh(Condition cond, Register rt, Label* label); void Ldrsb(Condition cond, Register rt, Label* label); void Ldrsh(Condition cond, Register rt, Label* label); void Vldr(Condition cond, DataType dt, DRegister rd, Label* label); void Vldr(Condition cond, DataType dt, SRegister rd, Label* label); ~~~ In short, we cannot guarantee that the label will be in range, and when using the macro-assembler, the user should have this guarantee. The only way to generate these instruction is through the creation of literals. Change-Id: I15be8d5d8a7a0b21987cb6ff767530446a615bbc
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
fb37b5d8438252728469290fa35a779817faea00 |
|
18-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Add tests for pool blocking in nested ExactAssemblyScope On top of adding tests, this patch adds a new top-level MacroAssembler::ArePoolsBlocked() API method. This is useful for testing that the pools are actually blocked or not, and that nesting does not accidentally unblock them. Change-Id: If3845c6686ef45ddf1d28b8876ffd349731cdd9d
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
5c01c410ae559d0a77d68a023957c5bc9de143e0 |
|
18-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Remove Adr(Register, Label*) support from the MacroAssembler The Adr macro-instruction taking a label should, in theory, be able to handle a label bound anywhere in the 32-bit address space. However this is not implemented therefore we shouldn't have it exposed in the MacroAssembler as it can be misleading. One would naturally expect it to generate the appropriate sequence for any label. Let's enable this again later once it is entirely implemented. Change-Id: I186b5f0ba1be4febb26ca548df2e1c056863e975
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
32929a7f73c3a103a2abe21f49258fba149a5157 |
|
18-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
Remove Switch implementation from VIXL The Switch implementation is not well tested, and uses Adr with a label which we are going to temporarily disallow until we support patching multiple instructions. The reason this is tricky is that pools can be generated in between each macro-instruction and this can break Adr, which breaks Switch. Let's add it again later when the feature is ready. Change-Id: I30d6adf89e4ddcebada6aa70ff7b6a5dc9239ad4
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
d56f609907e454dd41bb8b2d98e078e69c4feafa |
|
11-Jan-2017 |
Pierre Langlois <pierre.langlois@arm.com> |
ExactAssemblyScope: Force the pools not to be emitted There was a bug where the AArch32 MacroAssembler would still generate pools inside ExactAssemblyScope. In order to avoid this, this patch renames the `kCheckPools` policy to `kBlockPools`. Saying "check" implies we only assert that pools are not generated, which is not the case. Change-Id: Ica717f56f99c7363add5361076174e8e827dd81c
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
9a9331faeba996d6c85e6e2a6355ccfc22c6cab6 |
|
09-Dec-2016 |
Rodolph Perfetta <rodolph.perfetta@arm.com> |
Allow conditional inclusion of A32, T32 and A64. The 'target_arch' option has been replace by 'target' which can be any combination of aarch32, aarch64, a32, t32, a64. Change-Id: Id5cd052276747cd718551f562b74f79443b91869
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
a4cbc576a003da934ab58b293d9023d9b6f3077b |
|
05-Jan-2017 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix veneer emission. Change-Id: I2ef8b153f1ab87fa9972f80b1b4660ceefabceb4
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
80b4a1f554a92b2c4d4504265d0bac545c74c69b |
|
14-Dec-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Optimize add/sub with a big constant. Change-Id: I4d5e684fc9cb6a2fe754acfc3b75eb7b530273e2
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
0cc43be9ba1881f608a25467b1387927af3b4caa |
|
22-Dec-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Revert "[aarch32] Dot not abort when one uses unpredictable or strongly discouraged instructions" This reverts commit d836966fcbe0ec3136486ec36de6bd2572d451eb. Change-Id: I3e8b0ea9bc43594ab3ad569e54f78e00593dfea8
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
d836966fcbe0ec3136486ec36de6bd2572d451eb |
|
19-Dec-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
[aarch32] Dot not abort when one uses unpredictable or strongly discouraged instructions Calling VIXL_ABORT when a MacroAssembler object would call AllowUnpredictable or AllowStronglyDiscouraged would prevent us from handling those cases in delegates. It should be up to a delegate to decide whether to give the user an error or generate an alternative code sequence. Additionally, the user is able (but that's not recommended of course) to lift the UNPREDICTABLE or STRONGLY DISCOURAGED limitation using scopes. Since the AllowUnpredictable() and AllowStronglyDiscouraged() methods were virtual and overriden by the macro-assembler to abort. There was no way to write the following code: ```c++ MacroAssembler masm(T32); { ExactAssemblyScope scope(&masm, ...); AllowUnpredictableScope allow_unpredictable(&masm); // Here be dragons! } ``` This patch fixes this by turning AllowUnpredictable() and AllowStronglyDiscouraged() into non-virtual methods. Finally, the related scopes were inside the `aarch32::Assembler::` namespace, which is inconsistent with other scopes. Move it to `aarch32`. Change-Id: I42e5b772e850a8c23521385cf399aaae77b5eab6
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
a576eb92e2a877984e6e5c1e409e23c49c8b96a1 |
|
13-Dec-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Add more identities. Change-Id: I52ff78a7b101de88146ead71b555a17541f9b863
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
e8ce9f0ec7fe9484fca0c446ecc8a9d7929bea66 |
|
14-Dec-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Assert perfect nesting for UseScratchRegisterScope. Since UseScratchRegisterScope now has a MacroAssembler pointer anyway, this patch also removes available_ and availablefp_, and uses the MacroAssembler directly. Some negative tests would be useful but I'll add them separately. Change-Id: Ia093c67a980044f8e1514cff81998fd9dbfaa44e
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
1091d74cee7404c902fccdc6dba81609bbbdf443 |
|
16-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Generate ADD and not ADDS for Add(DontCare, r1, r1, r2). Change-Id: Iabb680bcd7b4027602ca48c34691d61d75b1e0af
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
5ddbc800588cde7e4d02f9fb7ca2f9e8c12522ef |
|
16-Dec-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Optimize IsModifiedImmediate and Orn/Orns delegate. Change-Id: I05ac177e9ef28a99dc00b43a2de6d7fdfae87ef3
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
be9c4d02c96eaa6cdc9a9a5ae3cc65f57d54585c |
|
15-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Support conditional load literal for T32. Change-Id: I2865cd2ef2e075c47d1d18838c97c04c9294177c
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
cf91ee6bcaabf00356516bbc2d478acbeb8bed9a |
|
13-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Make rewinding of load literal instructions less conservative. Change-Id: I2f1b7dce445ceff1edb1f93608b693737be1bc51
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
50e45c514c11300c91b370c251235a9a77bdaf5f |
|
13-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
After rewinding a load, only add the label to the literal pool if it's not bound. Change-Id: I5f0296582630cc8f81a72a304986b1c15acab02c
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
4f002a865b625dc388e9175bfdda285812e17f2b |
|
14-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Increase max recursion limit for delegates. The new case that needs a larger recursion limit is related to literal loads with negative offsets (due to already bound labels). In some cases, the Ldrd delegate (1) calls MemOperandComputationHelper which calls Add (2). The Add has a negative immediate that cannot be encoded so calls Sub (3). This recurses in the new code that handles add/sub with negative offsets (4), and after we recurse we add a Mov and end up in that Delegate (5). This increases the limit to 6 which works fine in this case. Change-Id: I994dd46a201fb24afb377bd13c4e5dcd3cb29002
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
4a30c5d68ebbc271d6d876d828ffa96db53d8d7c |
|
08-Dec-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Add MacroAssembler B with hint. Change-Id: Ic56a63c5af35c6d46b1a03a4b58165e991afc4d7
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
e31fda5ecc961cdb78a0a5311d692ae4b15e5933 |
|
13-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Correct number of bytes we check we can emit in ITScope. This value was out of sync with MacroEmissionCheckScope, and we are always using an ITScope together with a MacroEmissionCheckScope, so we could potentially trigger an assertion that was not necessary. Change-Id: I1e942d6b919070a3a41d4b38edde74feebb7cc19
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
9ae5da2ba518573576cc92e93e7a01dd34c8d1f7 |
|
05-Dec-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Specify instructions which use a delegate. Change-Id: I47b2ed73eab09d5ed6541073d571300e2fcdeef0
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
dd8e491930b4eb5928f0dec2441c69a471724ce5 |
|
12-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Generate 16-bit ADDS/SUBS for DontCare SUB/ADD with suitable immediates. Change-Id: Ia2c11ad7ac8b14c8d04881ed6b872ae2af7dd3d6
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
4443cf950cac7b0cf8e82196e60c26f4b2799a97 |
|
08-Dec-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Tests for 16-bit T32 instruction generation for DontCare flags update. This also fixes a few cases where we were failing to generate a 16-bit instruction. The issues fixed were resulting in sub-optimal instructions being generated, but they were not correctness issues. Change-Id: I3042165eeac90674b89a15db7b7c065925bdd30c
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
89d2f7702f0dc1751574bd5f9d35b5182fc65fac |
|
08-Dec-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Fix very-long-range literal loads. The code was basically functional but the CodeBufferCheckScope sizes had to be increased. The generated code could be improved, but its a corner case anyway so it's not a priority for now. Here's an example: 0x004223f2 f2af31ec adr r1, 0x00422008 0x004223f6 f44f5c00 mov ip, #8192 0x004223fa f2c00c42 movt ip, #66 0x004223fe eba1010c sub r1, ip 0x00422402 6809 ldr r1, [r1] This sequence occurs for offset ranges over about 1MB. For ranges below 1MB, the worst case is still adr+sub+ldr. Change-Id: I6345127aed12abb59c819f63167170d57160da0b
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
356323a3dbec6b302b7882ed8cf46e9457217d01 |
|
25-Nov-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Check that we don't generate deprecated IT instructions. Change-Id: If276f5f4f25408178b8a522ea1eb0c06707d0cfd
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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1ddc52b438c2f07872e6e715c6b86e8d3b772795 |
|
08-Dec-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix MacroAssembler::GenerateInstruction. Change-Id: Ibc942d3a8c3864f58a4f6d812864051b2d76bb59
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
bd087d8fe70f7db770f37569073b8b9f77a9c372 |
|
29-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix concurrent veneer and literal emission. Change-Id: I83be782d9e2862cb94ab618440c375a66c1da201
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
9c112d81bf7bc65d6bea5a1d889ef3db7609771d |
|
08-Dec-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Fix literal loads from unaligned instructions. Change-Id: I07a1f7819328ef7ce1fb36ccdc0b940312e36afb
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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f8c2284645ce651f99ba410a512279102851076e |
|
29-Nov-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Fix Ldr for distant, bound literals. Change-Id: I0ed3b1df4e93cbbc4bd5ce109130d1ce1ac35ef0
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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4c5d65bf4d3a5fcc6ccb5cd19fed81e2b735789b |
|
06-Dec-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Include AllowMacroInstructions methods in release mode The SetAllowMacroInstructions and AllowMacroInstructions methods were only included if VIXL_DEBUG was defined. While this is understandable, these methods are virtual and part of the MacroAssemblerInterface, which means the vtable of macro-assemblers has a different layout depending on VIXL_DEBUG. This can produce strange errors when headers are used incorrectly by the user, for instance if linking with a library compiled with VIXL_DEBUG defined by mistake. Additionally, this patch explicitely marks overriden methods of the MacroAssemblerInterface as virtual, as well as adding missing "internal" namespaces for AssemblerBase. Change-Id: I2f4595bd5990c944381b177809853e33354e9244
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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9ee25b5df54608e45947a7f99f2c23ce61802474 |
|
02-Dec-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
Add Exclude(const Operand&). This is useful for the common pattern of including destinations only if they don't alias the input: temps.Include(rd); temps.Exclude(rn); temps.Exclude(operand); Change-Id: Ibc3af5447b8fb22d92f3b7dc55daf3b608c8e8d6
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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000f93f0af01f9a3f250ad8fb8cd7a42e7b31c99 |
|
01-Dec-2016 |
Baptiste Afsa <baptiste.afsa@arm.com> |
aarch32: Add a few assertions in code dealing with literals. Change-Id: Idce680b4f7b98fa1fadfdbc079783e05aa01c3f0
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
1661f51a172e7c3dcce6caca55b6fe6d10ebd416 |
|
31-Oct-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Use the shared code generation scope `ExactAssemblyScope`. This patch finishes the transition to shared code generation scopes for the AArch32 backend. Change-Id: Iccbdb5de48b41803408410a01307afabe30a7fee
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
8d191abf32edf41421f68f35585e4fce8da4d50c |
|
29-Nov-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Use the shared scopes `CodeBufferCheckScope` and `EmissionCheckScope`. This patch continues toward the goal of unifying code-generation scopes for all backends. The new scopes differ from the existing AArch32 mechanisms, so a few tests for literal and veneer pools needed to be updated. The patch also adds AArch32 tests for the new scopes. Change-Id: Ia6a93e6e860b47e703b6c9034fefa405810c18a0
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
d17e348e16bf0d6eca4f9ea0e935c7544098d045 |
|
23-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Add unpredictable conditions for ADC_i, ADC_r, ADC_rr, ADD_ADR, ADD_i, ADD_r, ADD_rr, ADD_SP_i, ADD_SP_r, ADR and MOV_i. Change-Id: I2d0255c352881d855b375db65794ee7f282b1cfe
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
e7a1690b45036db4c2730ab1c2699ca764a40a68 |
|
23-Nov-2016 |
Georgia Kouveli <georgia.kouveli@arm.com> |
Add tests for generating IT blocks with the MacroAssembler. This also disallows generating an IT block for ROR (immediate), as there is no 16-bit T32 encoding for this instruction. Change-Id: Id4e9f3abc753b034219eeec6aad7a973cd5be69a
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
adbb4a746d2d90dd2920a8e0b7cd2397e93d17b9 |
|
22-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Remove inheritance of Register for RegisterOrAPSR_nzcv. Change-Id: Ie4baa104e243dc96bdf9f7d859597487ca62413b
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
989663e3cb7be8ac458d71f8e8d99afd29b13a39 |
|
24-Nov-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Rename operand-aarch32.{h,cc} to operands-aarch32.{h,cc} We were inconsistent in naming this file between the AArch64 and AArch32 targets, let's go with what AArch64 calls is and pluralize operand. Change-Id: Id2581255e4aa398f2c6fa81e5abce1f4b9b8a364
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
0eb25b040732354c6273c93df709f8d585a140de |
|
22-Nov-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Fix and test the precision of margins before pool emission. This precision is paramount when writing tests for corner cases of veneer or literal pools emission. Also check that the buffer only grows when required. Change-Id: I8992f1c389578a7a8301ea621ea6db7a7f9c9c11
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
b44f7a6ee7f9cd194cde9577f5a941f2864795a4 |
|
17-Nov-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Remove delegate support for load/store exclusive and pld This patch removes delegates that were trying to handle the following instructions: - pld - pldw - pli - lda - ldab - ldaex - ldaexb - ldaexh - ldah - ldrex - ldrexb - ldrexh - stl - stlb - stlh - ldaexd - ldrexd - stlex - stlexb - stlexh - strex - strexb - strexh - stlexd - strexd Instead, the user will get an error if they are used incorrectly. We no longer try to make them work with addressing modes that are not already supported by the instruction itself. Instead of having the delegates use VIXL_ABORT_WITH_MSG directly, I've changed the `UnimplementedDelegate` method to print the message "Ill-formed '{}' instruction.". To do this, we now have a `ToCString(InstructionType)` function to print instructions, defined in a new file "aarch32/constants-aarch32.cc". Change-Id: I4e1f955576b88aae3edaf4dad157f11d4755e6ca
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
fd7a00db313b38f1b328c7fc6af1325d85bc31ad |
|
09-Nov-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Do not force alignment in `MacroAssembler::EnsureEmitFor()`. The alignment requirements are relegated to users. The automatic alignment otherwise interferes when trying to control precisely the size of code we want to emit. Change-Id: I9a7eb509344c390ce9b91d3c687f6e56d38ab889
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
40b7e470e71b158158ef6ce8a1a3f701857ce0e2 |
|
09-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix PerformEnsureEmit for literals. Change-Id: Iab0cb33eb59a69a90a00754263c7210b16ad2044
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
cf4d2842eb8d63c621d7003e240ec094a357cad0 |
|
15-Nov-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
AArch32: Check that the user doesn't pass in scratch registers. The user must not use registers that the MacroAssembler can allocate as scratch registers. This patch attempts to enforce this restriction by checking that the user never passes an available scratch register to the MacroAssembler. Change-Id: I7897b788df6dc0fabc452df0fe28d986fd84097c
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
7827144797ee5ebfa0b574f45ad8ff235f919304 |
|
08-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Allow a label which is in the veneer pool to be bound with 'bind'. Change-Id: I1e0d03498ec86ed23d94ef1db2d2adc5b73ef984
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|
4634a88b6db240a13adc66f26ff3437806f08aec |
|
14-Nov-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Remove Addw, Movw, Subw, Tbb and Tbh from the MacroAssembler This patch removes instructions that should not be exposed to the user, instead, the MacroAssembler can choose to generate them. For instance: - Use Add/Mov/Sub instead of Addw/Movw/Subw. The latter instructions just target a specific encoding, they are for the assembler only. - Use Switch/Case/End to generate Tbb and Tbh instruction if they are available. This patch also removes references to these instructions in the macro-assembler's delegates as well as simulator tests for them. Of course, they are still covered by assembler tests. Change-Id: I86d606f433aad8cdccba8dd9681ff6d94a9adac3
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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4e329d4f71bb1a2f4dafca04a512e7c2862343f7 |
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15-Nov-2016 |
Martyn Capewell <martyn.capewell@arm.com> |
Remove masm support for vld3/vst3 This covered only vld3 and vst3 for single or all lanes (not multiple lanes) and was untested. It seems more prudent to remove this than complete the support for other vld/vst instructions, with tests. Change-Id: I707a0f2329ea530d16b64aa9062774e4de1c755d
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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21d8d8d551fc50cb15fc137f00a154ea65eb2b81 |
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14-Nov-2016 |
Martyn Capewell <martyn.capewell@arm.com> |
Improve error reporting in macro asm ContextScope Wrap ContextScope creation in a macro, and pass in the file and line number. These locations are printed out when a recursion limit is reached. Change-Id: Ia1339af9af146cf3682d9dc7bf2b131bea4524bf
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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f8833fa525b25cb1d72beb4f2d033d5ad9a3eb80 |
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09-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Allow Cbz/Cbnz to branch immediately after the instruction. Change-Id: I7ad6bbc84d69bc7ac3b61999fd77823b6ea552a2
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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76887c1820d5a7c957135c94e7cd57e39084ba8d |
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10-Nov-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Add comment to MacroAssembler::ContextScope. Change-Id: I8c7da6fef2456d61a4d3d3abbbd02103d2365249
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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aaac397e490f27ca3011e8ba2cb61f4f455c1a4d |
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09-Nov-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
AArch32: Replace uses of EnsureEmitFor with scopes. The intention is to catch cases where we generate more code than we have reserved space for. It is likely that many of these scopes reserve insufficient size, but they all pass the tests that exist. We still need to review each one, write tests, and update the sizes as appropriate. Note that EmissionCheckScope is the proper scope to use, but it isn't implemented consistently for AArch32 yet. However, it will be easy to replace these uses of CodeBufferCheckScope with EmissionCheckScope once it is available. Change-Id: Ie852c3688b2ae5b1b531d531ad1c2357808fb1eb
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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4e6b4af20e5664c43ca1717b4fa7d6fb4cb3667c |
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08-Nov-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Fix `MacroAssembler:VeneerPoolIsEmpty()`. Change-Id: I8a11f954e70fffe795336831a35eb3ee671c8a09
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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e42218c6ca969b7d4032da978fb05f06641df100 |
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19-Oct-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Make bind and place more consistent. Change-Id: I1743511e3c6f995f05cded38347a015c198b1fb9
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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dcffac4d0a5a586d3c14971e33bd28fc848bc148 |
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19-Oct-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Fix veneer/pool emission while in a Delegate. Change-Id: I76ff3e224f5e85a58a53865c62536d97e73b6730
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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3fac43c1a101f98f116e752b80abc122d32b83ac |
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31-Oct-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Mark methods as `override` when compiling with C++11 This patch introduces a VIXL_OVERRIDE macro. When building with gcc -std=c++11, we now enable the `-Wsuggest-override` warning so that we do not forget to add them in the future. Change-Id: I0f402599019ba9de1a7a654e9499f00a07f00201
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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25e3987b3b684df88edc8069d60b483b95587be5 |
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20-Oct-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Support getting the address of a literal with ADR This patch changes the printf implementation in the MacroAssembler to use ADR instead of LDR to get the address of the format string. The format string is placed directly in the code stream. Additionally, Literal<const char*> was changed to simply StringLiteral. It may be surprising to have a completely different behaviour for this case. Change-Id: I15c7acd457eb8ffed056a60cc438b9d7b54a94e1
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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919e3fe28a5024c53ede42922092bbc32e89dcb8 |
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14-Oct-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Create a base class for assemblers. This base class defines an interface that assemblers must adhere to. For now, we use it to hold the code buffer. Change-Id: I487430bb98c7044e57b348cffa1e74a2a4c8026f
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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e2aa8941a5b41fbd9f855906b8663009eac14669 |
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13-Oct-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
add some identities and macro-assembler rules Change-Id: I8f0b03e829a73024d73955d9abcee032e22fceb8
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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f5348cedd702124c90fc75e75d0195e2e485c620 |
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22-Sep-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Remove implicit 64 to 32 bit narrowing This patch fixes cases of implicit 64 to 32 bit narrowing. The issue is that `CodeBuffer` represents code offsets with `ptrdiff_t`, which will be 64 bit on a 64 bit system. However, we want to support generating 32 bit code from a 64 bit program, therefore the 32 bit part of VIXL works with `int32_t` for code offsets. We had implicit conversions happening due to this. We solve this by explicitely casting to `int32_t` in the AArch32 assembler when calling `GetCursorOffset`. If you are working with the `CodeBuffer` directly, you are dealing with a code buffer on the host and so will work with offsets as `ptrdiff_t`. But, when working with the AArch32 assembler itself you will get offsets as `int32_t`. The assembler is in charge of checking that the offsets it gets from the code buffer fit into `int32_t`. Additionally, we had narrowing cases when generally wrapping host pointers into an Operand. This can only work if the pointer fits into 32 bits. This patch introduces a Operand::From() factory method that can be used for converting any integral or pointer type to an immediate operand. Change-Id: Icc15711b34c2477ed997eef238e25496d86ea9aa
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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51d1cccb2cbb843c41a586fbedad00ded8f0d6a0 |
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22-Sep-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
add load functions with manually placed literals Change-Id: I60c554b2396c608ca371a427d718fe69892bfa26
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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628c5263f1ff96c793173770b85b93ebf8bf8d44 |
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21-Sep-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
AArch32: Optimise a few logical and arithmetic identities. The identities are used to avoid generating code or for strength reduction. Change-Id: I8eecd23ced2b283884651a49e794c8f34bda1d29
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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f678618ae35a43dab65455f446c3de324994c204 |
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21-Sep-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Add generic VFP functions which use VRegister instead of SRegister or DRegister. Change-Id: I686e05ec11346711939b58be3730067021f7df72
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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d2d8c09008ae28805b862ae7c79183db1ad50e9b |
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19-Sep-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
remove It instruction from the macro assembler Change-Id: I8676d3be1e69da3fa27f84e932401467dee92635
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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8885c17bce593f82cf90c086da242e52943c50ef |
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24-Aug-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
forbid direct use of assembler from the macro-assembler Change-Id: Ic00c9c72e9aed7efaab72a6fd6838bbd0bda6531
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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934696dd32c579b5a8aa80bae5384be22f0d9b9c |
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18-Aug-2016 |
Vincent Belliard <vincent.belliard@arm.com> |
Allow specifying whether an instruction should set flags with an `enum` This patch allow the macro-assembler user to call instructions which can set flags with an argument. That is instead of calling "add(rd, ...)" or "adds(rd, ...)" you can call "add(flags, rd, ...)" with flags which can take the values: - SetFlags - LeaveFlags - DontCare It will call the right function (add or adds) depending on flags and the context. Change-Id: I46d07d3b2989522d16d6432a469dc4b796682cbd
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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1e85b7f2e8ad2bfb233de29405aade635ed207ce |
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05-Aug-2016 |
Pierre Langlois <pierre.langlois@arm.com> |
Introduce architecture specific guards for the simulator This patch makes the VIXL_INCLUDE_SIMULATOR and VIXL_GENERATE_SIMULATOR_CODE header guards specific to either AArch64 or AArch32. Even though the simulator only support AArch64. The build system was updated accordingly, the "simulator" variable now takes "aarch64" or "none" as possible values instead of "on" and "off". This fixes issues we have when we want to build VIXL natively on AArch64 without a simulator, but still include the AArch32 macro-assembler. The later would check for VIXL_GENERATE_SIMULATOR_CODE and then generate calls to native code, which breaks. Change-Id: I2850782558d4cc37f37c1644f0efbd70a3123057
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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fd09817b8770a5e3a64a6fe4fefe85cc29805cd7 |
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09-Aug-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Do not include data members conditionally on `VIXL_DEBUG` in headers. Objects visible via headers should have the same data-layout in release and debug modes. Change-Id: I7ce5014ab8406968cdd8e9818a7f840cb443b6c1
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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10dae1a549308bddc1931f29754d6a4459f70c9b |
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27-Jul-2016 |
Jacob Bramley <jacob.bramley@arm.com> |
AArch32: Improve the API for selecting the ISA. Specifically, replace SetT32(false) with SetA32(), and SetT32(true) with SetT32(). This also adds a parameterised SetInstructionSet(...) helper, and allows the instruction set to be set in the constructors. Change-Id: I82609823a4b2af908b38c0a4240ff239561f7507
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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ad91cee685f33b45841b95999ea0a0eb2c3f9708 |
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26-Jul-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Minor fix to a comment for Claim(), Drop(), and Peek(). Change-Id: I7c80121610c99bf3114af7644450209cfdb215cb
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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703ff06a087f67fccde24a7ffbc8a2e74a406cb1 |
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11-Jul-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Aarch64: Rename `allow_simulator_instructions_` to `generate_simulator_code_`. Change-Id: I72956db90ab3380b5ad62b37d2ed203ec4045931
/external/vixl/src/aarch32/macro-assembler-aarch32.h
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d3832965c62a8ad461b9ea9eb0994ca6b0a3da2c |
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04-Jul-2016 |
Alexandre Rames <alexandre.rames@linaro.org> |
Update naming to `aarch32` and `aarch64`. Change-Id: I40a929b1095ee3e1b2ca5ef879c7006d8b59acc9
/external/vixl/src/aarch32/macro-assembler-aarch32.h
|