Searched defs:DefMI (Results 1 - 25 of 46) sorted by relevance

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/external/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, argument
30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
45 MachineInstr *DefMI = LastMI; local
58 DefMI = &*I;
62 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
64 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
H A DMLxExpansionPass.cpp95 MachineInstr *DefMI = MRI->getVRegDef(Reg); local
97 if (DefMI->getParent() != MBB)
99 if (DefMI->isCopyLike()) {
100 Reg = DefMI->getOperand(1).getReg();
102 DefMI = MRI->getVRegDef(Reg);
105 } else if (DefMI->isInsertSubreg()) {
106 Reg = DefMI->getOperand(2).getReg();
108 DefMI = MRI->getVRegDef(Reg);
114 return DefMI;
149 MachineInstr *DefMI local
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMHazardRecognizer.cpp19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, argument
30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
48 MachineInstr *DefMI = LastMI; local
58 DefMI = &*I;
62 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
64 hasRAWHazard(DefMI, MI, TRI))) {
H A DMLxExpansionPass.cpp92 MachineInstr *DefMI = MRI->getVRegDef(Reg); local
94 if (DefMI->getParent() != MBB)
96 if (DefMI->isCopyLike()) {
97 Reg = DefMI->getOperand(1).getReg();
99 DefMI = MRI->getVRegDef(Reg);
102 } else if (DefMI->isInsertSubreg()) {
103 Reg = DefMI->getOperand(2).getReg();
105 DefMI = MRI->getVRegDef(Reg);
111 return DefMI;
160 MachineInstr *DefMI
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/external/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp126 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1); local
130 if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) {
131 unsigned FeedImmed = DefMI->getOperand(3).getImm();
133 = lookThruCopyLike(DefMI->getOperand(1).getReg());
135 = lookThruCopyLike(DefMI->getOperand(2).getReg());
156 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg());
157 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg());
169 .addOperand(DefMI->getOperand(1));
H A DPPCVSXSwapRemoval.cpp614 MachineInstr* DefMI = MRI->getVRegDef(Reg); local
615 assert(SwapMap.find(DefMI) != SwapMap.end() &&
617 int DefIdx = SwapMap[DefMI];
624 DEBUG(DefMI->dump());
694 MachineInstr *DefMI = MRI->getVRegDef(UseReg); local
695 unsigned DefReg = DefMI->getOperand(0).getReg();
696 int DefIdx = SwapMap[DefMI];
706 DEBUG(DefMI->dump());
712 // Ensure all uses of the register defined by DefMI feed store
724 DEBUG(DefMI
770 MachineInstr *DefMI = MRI->getVRegDef(UseReg); local
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H A DPPCInstrInfo.cpp142 const MachineInstr &DefMI, unsigned DefIdx,
145 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
148 if (!DefMI.getParent())
151 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
157 &DefMI.getParent()->getParent()->getRegInfo();
167 Latency = getInstrLatency(ItinData, DefMI);
1213 bool PPCInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, argument
1217 unsigned DefOpc = DefMI.getOpcode();
1220 if (!DefMI.getOperand(1).isImm())
1222 if (DefMI
141 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const argument
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/external/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp72 MachineInstrBuilder &DefMI) {
81 DefMI.addOperand(MO);
71 transferImpOps(MachineInstr &OldMI, MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI) argument
/external/swiftshader/third_party/LLVM/lib/Target/
H A DTargetInstrInfo.cpp66 const MachineInstr *DefMI, unsigned DefIdx,
71 unsigned DefClass = DefMI->getDesc().getSchedClass();
114 const MachineInstr *DefMI,
119 unsigned DefClass = DefMI->getDesc().getSchedClass();
65 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
113 hasLowDefLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx) const argument
/external/llvm/lib/CodeGen/
H A DLiveRangeEdit.cpp52 const MachineInstr *DefMI,
54 assert(DefMI && "Missing instruction");
56 if (!TII.isTriviallyReMaterializable(*DefMI, aa))
69 MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def); local
70 if (!DefMI)
72 checkRematerializable(OrigVNI, DefMI, aa);
166 MachineInstr *DefMI = nullptr, *UseMI = nullptr; local
172 if (DefMI && DefMI != MI)
176 DefMI
51 checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI, AliasAnalysis *aa) argument
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H A DTargetSchedule.cpp155 const MachineInstr *DefMI, unsigned DefOperIdx,
159 return TII->defaultDefLatency(SchedModel, *DefMI);
164 OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx,
168 unsigned DefClass = DefMI->getDesc().getSchedClass();
175 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI);
183 std::max(InstrLatency, TII->defaultDefLatency(SchedModel, *DefMI));
187 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
188 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
211 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
212 && !DefMI
154 computeOperandLatency( const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const argument
215 << *DefMI << " (Try with MCSchedModel.CompleteModel set to false)"; local
268 computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *DepMI) const argument
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H A DDetectDeadLanes.cpp362 const MachineInstr &DefMI = *Def.getParent(); local
363 if (lowersToCopies(DefMI)) {
380 for (const MachineOperand &MO : DefMI.uses()) {
390 } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) {
407 unsigned OpNum = DefMI.getOperandNo(&MO);
412 if (DefMI.isImplicitDef() || Def.isDead())
516 // Transfer UsedLanes to operands of DefMI (backwards dataflow).
H A DMachineCSE.cpp132 MachineInstr *DefMI = MRI->getVRegDef(Reg); local
133 if (!DefMI->isCopy())
135 unsigned SrcReg = DefMI->getOperand(1).getReg();
138 if (DefMI->getOperand(0).getSubReg())
152 if (DefMI->getOperand(1).getSubReg())
157 DEBUG(dbgs() << "Coalescing: " << *DefMI);
164 DefMI->eraseFromParent();
H A DMachineSink.cpp175 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
176 if (DefMI->isCopyLike())
178 DEBUG(dbgs() << "Coalescing: " << *DefMI);
396 MachineInstr *DefMI = MRI->getVRegDef(Reg); local
397 if (DefMI->getParent() == MI.getParent())
H A DEarlyIfConversion.cpp245 MachineInstr *DefMI = MRI->getVRegDef(Reg); local
246 if (!DefMI || DefMI->getParent() != Head)
248 if (InsertAfter.insert(DefMI).second)
249 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI);
250 if (DefMI->isTerminator()) {
H A DTailDuplicator.cpp160 MachineInstr *DefMI = MRI->getVRegDef(VReg); local
162 if (DefMI) {
163 DefBB = DefMI->getParent();
/external/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp261 MachineInstr *DefMI = MRI.getVRegDef(Reg); local
263 assert(DefMI);
265 // See if DefMI is an instruction that loads from a GOT entry that holds the
267 if (!DefMI->mayLoad() || DefMI->getNumOperands() < 3)
270 unsigned Flags = DefMI->getOperand(2).getTargetFlags();
276 assert(DefMI->hasOneMemOperand());
277 Val = (*DefMI->memoperands_begin())->getValue();
279 Val = (*DefMI->memoperands_begin())->getPseudoValue();
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DLiveRangeEdit.cpp45 const MachineInstr *DefMI,
48 assert(DefMI && "Missing instruction");
50 if (!tii.isTriviallyReMaterializable(DefMI, aa))
64 MachineInstr *DefMI = lis.getInstructionFromIndex(VNI->def); local
65 if (!DefMI)
67 checkRematerializable(VNI, DefMI, tii, aa);
167 MachineInstr *DefMI = 0, *UseMI = 0; local
175 if (DefMI && DefMI != MI)
179 DefMI
44 checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI, const TargetInstrInfo &tii, AliasAnalysis *aa) argument
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H A DPHIElimination.cpp134 MachineInstr *DefMI = *I; local
135 unsigned DefReg = DefMI->getOperand(0).getReg();
137 DefMI->eraseFromParent();
176 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg); local
177 if (!DefMI || !DefMI->isImplicitDef())
297 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); local
298 if (DefMI->isImplicitDef()) {
299 ImpDefs.insert(DefMI);
H A DPeepholeOptimizer.cpp294 MachineInstr *DefMI = MRI->getVRegDef(Src); local
295 if (!DefMI || !DefMI->getDesc().isBitcast())
299 NumDefs = DefMI->getDesc().getNumDefs();
300 NumSrcs = DefMI->getDesc().getNumOperands() - NumDefs;
304 const MachineOperand &MO = DefMI->getOperand(i);
H A DMachineCSE.cpp125 MachineInstr *DefMI = MRI->getVRegDef(Reg); local
126 if (DefMI->getParent() != MBB)
128 if (!DefMI->isCopy())
130 unsigned SrcReg = DefMI->getOperand(1).getReg();
133 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
137 DEBUG(dbgs() << "Coalescing: " << *DefMI);
141 DefMI->eraseFromParent();
H A DScheduleDAGInstrs.cpp599 MachineInstr *DefMI = Def->getInstr(); local
600 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
602 const MachineOperand &MO = DefMI->getOperand(DefIdx);
604 DefIdx >= (int)DefMI->getDesc().getNumOperands()) {
611 DefIdx = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI);
625 int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx,
633 unsigned DefClass = DefMI->getDesc().getSchedClass();
/external/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp317 for (auto DefMI : List) {
319 int64_t AddrDispShiftTemp = getAddrDispShift(MI, MemOpNo, *DefMI, 1);
331 MRI->getRegClass(DefMI->getOperand(0).getReg()))
338 int DistTemp = calcInstrDist(*DefMI, MI);
348 BestLEA = DefMI;
487 MachineInstr *DefMI; local
490 if (!chooseBestLEA(LEAs[getMemOpKey(MI, MemOpNo)], MI, DefMI, AddrDispShift,
501 DefMI->removeFromParent();
502 MBB->insert(MachineBasicBlock::iterator(&MI), DefMI); local
503 InstrPos[DefMI]
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/external/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp501 MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI, this); local
502 bool Invert = !DefMI;
503 if (!DefMI)
504 DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI, this);
505 if (!DefMI)
515 // Create a new predicated version of DefMI.
517 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
519 // Copy all the DefMI operands, excluding its (null) predicate.
520 const MCInstrDesc &DefDesc = DefMI->getDesc();
523 NewMI.addOperand(DefMI
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/external/swiftshader/third_party/LLVM/include/llvm/Target/
H A DTargetInstrInfo.h620 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, argument
644 const MachineInstr *DefMI, unsigned DefIdx,
673 const MachineInstr *DefMI, unsigned DefIdx,
682 const MachineInstr *DefMI, unsigned DefIdx) const;
671 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument

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