Searched defs:Intf (Results 1 - 3 of 3) sorted by relevance
/external/llvm/lib/CodeGen/ |
H A D | RegAllocBasic.cpp | 179 LiveInterval *Intf = Q.interferingVRegs()[i - 1]; local 180 if (!Intf->isSpillable() || Intf->weight > VirtReg.weight) 182 Intfs.push_back(Intf);
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H A D | RegAllocGreedy.cpp | 269 InterferenceCache::Cursor Intf; member in struct:__anon12730::RAGreedy::GlobalSplitCandidate 278 Intf.setPhysReg(Cache, Reg); 753 LiveInterval *Intf = Q.interferingVRegs()[i - 1]; local 754 assert(TargetRegisterInfo::isVirtualRegister(Intf->reg) && 757 if (getStage(*Intf) == RS_Done) 766 (Intf->isSpillable() || 768 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg))); 770 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade; 779 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg); 782 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf 830 LiveInterval *Intf = Intfs[i]; local 934 addSplitConstraints(InterferenceCache::Cursor Intf, BlockFrequency &Cost) argument 998 addThroughConstraints(InterferenceCache::Cursor Intf, ArrayRef<unsigned> Blocks) argument [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | RegAllocGreedy.cpp | 190 InterferenceCache::Cursor Intf; member in struct:__anon19841::RAGreedy::GlobalSplitCandidate 199 Intf.setPhysReg(Cache, Reg); 543 LiveInterval *Intf = Q.interferingVRegs()[i - 1]; local 544 if (TargetRegisterInfo::isPhysicalRegister(Intf->reg)) 547 if (getStage(*Intf) == RS_Done) 552 bool Urgent = !VirtReg.isSpillable() && Intf->isSpillable(); 554 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade; 563 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg); 566 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight); 571 if (!Urgent && !shouldEvict(VirtReg, IsHint, *Intf, BreaksHin 597 LiveInterval *Intf = Q.interferingVRegs()[i]; local 672 addSplitConstraints(InterferenceCache::Cursor Intf, float &Cost) argument 730 addThroughConstraints(InterferenceCache::Cursor Intf, ArrayRef<unsigned> Blocks) argument [all...] |
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