| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCompound.cpp | 346 MCInst const &MIb, bool IsExtendedB) {
348 unsigned MIbG = getCompoundCandidateGroup(MIb, IsExtendedB);
356 (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg()));
345 isOrderedCompoundPair(MCInst const &MIa, bool IsExtendedA, MCInst const &MIb, bool IsExtendedB) argument
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| H A D | HexagonMCDuplexInfo.cpp | 573 MCInst const &MIb, bool ExtendedB,
580 unsigned Opcode = MIb.getOpcode();
585 MIbG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIb);
594 MCInst SubInst1 = HexagonMCInstrInfo::deriveSubInst(MIb);
608 if (MIb.getOpcode() == Hexagon::S2_allocframe)
613 // Note that MIb (slot1) can be extended and MIa (slot0)
620 if (subInstWouldBeExtended(MIb) && !ExtendedB)
624 // If jumpr r31 appears, it must be in slot 0, and never slot 1 (MIb).
626 if ((MIb.getNumOperands() > 1) && MIb
571 isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa, bool ExtendedA, MCInst const &MIb, bool ExtendedB, bool bisReversable) argument
645 isDuplexPair(MCInst const &MIa, MCInst const &MIb) argument
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| H A D | R600ControlFlowFinalizer.cpp | 337 MachineInstr *MIb = BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), local
341 return ClauseFile(MIb, std::move(ClauseContent));
557 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), variable
562 Pair.second.insert(MIb);
582 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), variable
586 IfThenElseStack.push_back(MIb);
587 DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
596 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), variable
600 DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
601 IfThenElseStack.push_back(MIb);
611 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), variable
615 (void)MIb; variable
630 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), variable
638 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), variable
[all...] |
| /external/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 90 MachineInstr &MIb,
93 assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
95 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
96 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
109 getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) {
89 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const argument
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64LoadStoreOptimizer.cpp | 1075 static bool mayAlias(MachineInstr &MIa, MachineInstr &MIb, argument
1078 if (!MIa.mayStore() && !MIb.mayStore())
1082 if (!MIa.mayLoadOrStore() && !MIb.mayLoadOrStore())
1085 return !TII->areMemAccessesTriviallyDisjoint(MIa, MIb);
1091 for (MachineInstr *MIb : MemInsns)
1092 if (mayAlias(MIa, *MIb, TII))
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| H A D | AArch64InstrInfo.cpp | 658 MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const {
665 assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
667 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
668 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
677 getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) {
657 areMemAccessesTriviallyDisjoint( MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const argument
|
| /external/llvm/include/llvm/Target/ |
| H A D | TargetInstrInfo.h | 1427 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, argument
1431 assert((MIb.mayLoad() || MIb.mayStore()) &&
1432 "MIb must load from or modify a memory location");
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| /external/llvm/lib/CodeGen/ |
| H A D | ScheduleDAGInstrs.cpp | 564 MachineInstr *MIb) {
568 assert ((MIa->mayStore() || MIb->mayStore()) &&
572 if (TII->areMemAccessesTriviallyDisjoint(*MIa, *MIb, AA))
580 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand())
584 MachineMemOperand *MMOb = *MIb->memoperands_begin();
562 MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI, const DataLayout &DL, MachineInstr *MIa, MachineInstr *MIb) argument
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1627 MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const {
1631 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1632 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
1637 if (MIa.mayLoad() && !isMemOp(&MIa) && MIb.mayLoad() && !isMemOp(&MIb))
1645 // Get base, offset, and access size in MIb.
1646 unsigned BaseRegB = getBaseAndOffset(&MIb, OffsetB, SizeB);
2026 const MachineInstr *MIb) const {
2028 HexagonII::SubInstructionGroup MIbG = getDuplexCandidateGroup(MIb);
1626 areMemAccessesTriviallyDisjoint( MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const argument
|