| de2d8694e25a814696358e95141f4b1aa4d8847e |
|
20-Sep-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r275480
Bug: http://b/31320715
This merges commit 7dcf7f03e005379ef2f06db96aa93f06186b66d5 from
aosp/dev.
Test: Build AOSP and run RenderScript tests (host tests for slang and
libbcc, RsTest, CTS)
Change-Id: Iaf3738f74312d875e69f61d604ac058f381a2a1a
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| f3ef5332fa3f4d5ec72c178a2b19dac363a19383 |
|
04-Mar-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r256229
http://b/26987366
Change-Id: I1f29c4676a8abe633ab5707dded58d846c973d50
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 6948897e478cbd66626159776a8017b3c18579b9 |
|
01-Jul-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r239765
Bug: 20140355: This rebase pulls the upstream fix for the spurious
warnings mentioned in the bug.
Change-Id: I7fd24253c50f4d48d900875dcf43ce3f1721a3da
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 4c5e43da7792f75567b693105cc53e3f1992ad98 |
|
08-Apr-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master llvm for rebase to r233350
Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| ebe69fe11e48d322045d5949c83283927a0d790b |
|
23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 050ed11bd691ea770273d8a6cd4acbd00ad75ccb |
|
09-Dec-2014 |
Tom Stellard <thomas.stellard@amd.com> |
MISched: Fix moving stores across barriers
This fixes an issue with ScheduleDAGInstrs::buildSchedGraph
where stores without an underlying object would not be added
as a predecessor to the current BarrierChain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223717 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
|
01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| c6a4f5e819217e1e12c458aed8e7b122e23a3a58 |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 5649e25ce86b9d89d228ae7c392413571b0f8c19 |
|
10-Oct-2013 |
Matthias Braun <matze@braunis.de> |
Pass LiveQueryResult by value
This makes the API a bit more natural to use and makes it easier to make
LiveRanges implementation details private.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 40b52bb8f2b4f63f6d99e347af0c48945f9cb4d2 |
|
04-Sep-2013 |
Andrew Trick <atrick@apple.com> |
mi-sched: bypass heuristic checks when regpressure tracking is disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189988 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 663bd9922776e5f7bc17dfc574efe3fe05ceb12c |
|
30-Aug-2013 |
Andrew Trick <atrick@apple.com> |
mi-sched: update PressureDiffs on-the-fly for liveness.
This removes all expensive pressure tracking logic from the scheduling
critical path of node comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189643 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 4c60b8a78d811a5b16ae45f6957933fb479bab58 |
|
30-Aug-2013 |
Andrew Trick <atrick@apple.com> |
mi-sched: Precompute a PressureDiff for each instruction, adjust for liveness later.
Created SUPressureDiffs array to hold the per node PDiff computed during DAG building.
Added a getUpwardPressureDelta API that will soon replace the old
one. Compute PressureDelta here from the precomputed PressureDiffs.
Updating for liveness will come next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 851bb2c9cbbd3b1847def5ca7ea8dadf457298b5 |
|
29-Aug-2013 |
Andrew Trick <atrick@apple.com> |
Comment and revise the cyclic critical path code.
This should be much more clear now. It's still disabled pending testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189597 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 738073c4aa474e27c9d3c991daf593bddce54718 |
|
29-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add useAA() to TargetSubtargetInfo
There are several optional (off-by-default) features in CodeGen that can make
use of alias analysis. These features are important for generating code for
some kinds of cores (for example the (in-order) PPC A2 core). This adds a
useAA() function to TargetSubtargetInfo to allow these features to be enabled
by default on a per-subtarget basis.
Here is the first use of this function: To control the default of the
-enable-aa-sched-mi feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| ea57433cee8bd59acaa99d148b45df92347cea68 |
|
23-Aug-2013 |
Andrew Trick <atrick@apple.com> |
Adds cyclic critical path computation and heuristics, temporarily disabled.
Estimate the cyclic critical path within a single block loop. If the
acyclic critical path is longer, then the loop will exhaust OOO
resources after some number of iterations. If lag between the acyclic
critical path and cyclic critical path is longer the the time it takes
to issue those loop iterations, then aggressively schedule for
latency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189120 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 99093638a024fc23609a323677e67bb1dc63ebe7 |
|
23-Aug-2013 |
Andrew Trick <atrick@apple.com> |
MI Sched: record local vreg uses.
This will be used to compute the cyclic critical path and to
update precomputed per-node pressure differences.
In the longer term, it could also be used to speed up LiveInterval
update by avoiding visiting all global vreg users.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189118 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| d2763f6ce62eaa497e944331668414e35f3712f3 |
|
23-Aug-2013 |
Andrew Trick <atrick@apple.com> |
mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr count.
This fixes a pathological compile time problem with very large blocks
and lots of scheduling boundaries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189116 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| f22fd3f7b557a967b1edc1fa9ae770006a39e97c |
|
03-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl instead of SmallVector for iterators and references to avoid specifying the vector size unnecessarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185512 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 04d5613162fb39649ab6a1e645864574d4836511 |
|
29-Jun-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
misched: Compress pairs returned by getUnderlyingObjectsForInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| b86a0cdb674549d8493043331cecd9cbf53b80da |
|
15-Jun-2013 |
Andrew Trick <atrick@apple.com> |
Machine Model: Add MicroOpBufferSize and resource BufferSize.
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize
These can be used to more precisely model instruction execution if desired.
Disabled some misched tests temporarily. They'll be reenabled in a few commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 4392f0f407fe4e2a9ec53b2560a1cbf86357c190 |
|
13-Apr-2013 |
Andrew Trick <atrick@apple.com> |
MI-Sched: schedule physreg copies.
The register allocator expects minimal physreg live ranges. Schedule
physreg copies accordingly. This is slightly tricky when they occur in
the middle of the scheduling region. For now, this is handled by
rescheduling the copy when its associated instruction is
scheduled. Eventually we may instead bundle them, but only if we can
preserve the bundles as parallel copies during regalloc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179449 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 91231a6dc7c10e05934f2cf141a2d66b604a528f |
|
12-Feb-2013 |
Sergei Larin <slarin@codeaurora.org> |
Equal treatment of labels and other terminators in MI DAG construction.
MI sched DAG construction allows targets to include terminators into scheduling DAG.
Extend this functionality to labels as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174977 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| c6ada8e5f38168f13830e448f2b9e2d8e3eac72b |
|
25-Jan-2013 |
Andrew Trick <atrick@apple.com> |
ScheduleDAG: colorize the DOT graph and improve formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173431 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| a5a73ad15905c18843a8312bb3f20f5c501744de |
|
25-Jan-2013 |
Andrew Trick <atrick@apple.com> |
ScheduleDAG: Added isBoundaryNode to conveniently detect a common corner case.
This fixes DAG subtree analysis at the boundary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173427 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 988d06b0e574d8e50b043fd74dbf91c1dc403542 |
|
25-Jan-2013 |
Andrew Trick <atrick@apple.com> |
SchedDFS: Complete support for nested subtrees.
Maintain separate per-node and per-tree book-keeping.
Track all instructions above a DAG node including nested subtrees.
Seperately track instructions within a subtree.
Record subtree parents.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173426 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 4e1fb1894048455d49d62543b3f83672b27b0000 |
|
25-Jan-2013 |
Andrew Trick <atrick@apple.com> |
MIsched: Improve the interface to SchedDFS analysis (subtrees).
Allow the strategy to select SchedDFS. Allow the results of SchedDFS
to affect initialization of the scheduler state.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| bfb8223e2b2a55c3ac6c73be0ac99bbce17cb097 |
|
25-Jan-2013 |
Andrew Trick <atrick@apple.com> |
SchedDFS: Initial support for nested subtrees.
This is mostly refactoring, along with adding an instruction count
within the subtrees and ensuring we only look at data edges.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173420 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| b12a77199245a72c24dadbc039ed263d68d8e91a |
|
25-Jan-2013 |
Andrew Trick <atrick@apple.com> |
SchedDFS: Refactor and tweak the subtree selection criteria.
For sanity, create a root when NumDataSuccs >= 4. Splitting large
subtrees will no longer be detrimental after my next checkin to handle
nested tree. A magic number of 4 is fine because single subtrees
seldom rejoin more than this. It makes subtrees easier to visualize
and heuristics more sane.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173399 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| afe77f33b2a361ed0d001596dcdde0e16d57abee |
|
21-Jan-2013 |
Michael Ilseman <milseman@apple.com> |
Introduce a new data structure, the SparseMultiSet, and changes to the MI scheduler to use it.
A SparseMultiSet adds multiset behavior to SparseSet, while retaining SparseSet's desirable properties. Essentially, SparseMultiSet provides multiset behavior by storing its dense data in doubly linked lists that are inlined into the dense vector. This allows it to provide good data locality as well as vector-like constant-time clear() and fast constant time find(), insert(), and erase(). It also allows SparseMultiSet to have a builtin recycler rather than keeping SparseSet's behavior of always swapping upon removal, which allows it to preserve more iterators. It's often a better alternative to a SparseSet of a growable container or vector-of-vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173064 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
|
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 04f52e1300f4eff5b5e5280fbf032f571854a539 |
|
18-Dec-2012 |
Andrew Trick <atrick@apple.com> |
MISched: add dependence to ExitSU to model live-out latency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170454 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| f21831073ca474601620d1a29258176b0deaedb2 |
|
10-Dec-2012 |
Hal Finkel <hfinkel@anl.gov> |
Use GetUnderlyingObjects in misched
misched used GetUnderlyingObject in order to break false load/store
dependencies, and the -enable-aa-sched-mi feature similarly relied on
GetUnderlyingObject in order to ensure it is safe to use the aliasing analysis.
Unfortunately, GetUnderlyingObject does not recurse through phi nodes, and so
(especially due to LSR) all of these mechanisms failed for
induction-variable-dependent loads and stores inside loops.
This change replaces uses of GetUnderlyingObject with GetUnderlyingObjects
(which will recurse through phi and select instructions) in misched.
Andy reviewed, tested and simplified this patch; Thanks!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169744 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
|
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 657b75b9946eae763725b413841dfd01ed12a051 |
|
01-Dec-2012 |
Andrew Trick <atrick@apple.com> |
misched: Fix RegisterPressureTracker handling of DebugVals.
Assertion failed: (TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker").
rdar://12790302.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169072 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 177d87ac8d974529b07430b2088f699ed279cd1d |
|
01-Dec-2012 |
Andrew Trick <atrick@apple.com> |
misched: Fix the DAG builder to handle an undef operand at ExitSU.
Assertion failed: (VNI && "No value to read by operand")
rdar://12790267.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169071 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 8b1496c922b6a21296f7d42172df45bf205d5419 |
|
28-Nov-2012 |
Andrew Trick <atrick@apple.com> |
misched: Analysis that partitions the DAG into subtrees.
This is a simple, cheap infrastructure for analyzing the shape of a
DAG. It recognizes uniform DAGs that take the shape of bottom-up
subtrees, such as the included matrix multiplication example. This is
useful for heuristics that balance register pressure with ILP. Two
canonical expressions of the heuristic are implemented in scheduling
modes: -misched-ilpmin and -misched-ilpmax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 53e98a2c4aa7065f4136c5263b14192036c1e056 |
|
28-Nov-2012 |
Andrew Trick <atrick@apple.com> |
misched: rename ScheduleDAGILP to ScheduleDFS to prepare for other heuristics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168772 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 8f82a0867343058f4e01d640abbfae76af6886b4 |
|
28-Nov-2012 |
Andrew Trick <atrick@apple.com> |
misched: better alias analysis.
This fixes a hole in the "cheap" alias analysis logic implemented within
the DAG builder itself, regardless of whether proper alias analysis is
enabled. It now handles this pattern produced by LSR+CodeGenPrepare.
%sunkaddr1 = ptrtoint * %obj to i64
%sunkaddr2 = add i64 %sunkaddr1, %lsr.iv
%sunkaddr3 = inttoptr i64 %sunkaddr2 to i32*
store i32 %v, i32* %sunkaddr3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 009cf9e9a3a386f89db2686a105736481aed10ca |
|
15-Nov-2012 |
Sergei Larin <slarin@codeaurora.org> |
Fix indeterminism in MI scheduler DAG construction.
Similarly to several recent fixes throughout the code replace std::map use with the MapVector.
Add find() method to the MapVector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168051 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| ae692f2baedf53504af2715993b166950e185a55 |
|
12-Nov-2012 |
Andrew Trick <atrick@apple.com> |
misched: Infrastructure for weak DAG edges.
This adds support for weak DAG edges to the general scheduling
infrastructure in preparation for MachineScheduler support for
heuristics based on weak edges.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| a78d3228e8b2a14915ea9908dbaaf2c934803e11 |
|
06-Nov-2012 |
Andrew Trick <atrick@apple.com> |
ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.
This is in preparation for adding "weak" DAG edges, but generally
simplifies the design.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167435 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 3d71688476951d56ac00a81b17c2f83fd781b208 |
|
30-Oct-2012 |
Chad Rosier <mcrosier@apple.com> |
[inline asm] Implement mayLoad and mayStore for inline assembly. In general,
the MachineInstr MayLoad/MayLoad flags are based on the tablegen implementation.
For inline assembly, however, we need to compute these based on the constraints.
Revert r166929 as this is no longer needed, but leave the test case in place.
rdar://12033048 and PR13504
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| a836563e3208ad0b74019dc33ad361d3eb72f178 |
|
29-Oct-2012 |
Preston Gurd <preston.gurd@intel.com> |
This patch addresses a problem with the Post RA scheduler generating an
incorrect instruction sequence due to it not being aware that an
inline assembly instruction may reference memory.
This patch fixes the problem by causing the scheduler to always assume that any
inline assembly code instruction could access memory. This is necessary because
the internal representation of the inline instruction does not include
any information about memory accesses.
This should fix PR13504.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 6b0db5f372057745c5e4a99d70401dc2615cc084 |
|
26-Oct-2012 |
Nick Lewycky <nicholas@mxc.ca> |
Fix typo in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166750 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 1e94e98b0ec44c5b04eaa8c9e7fb6d7669b3cdea |
|
15-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: ILP scheduler for experimental heuristics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165950 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 412cd2f81374865dfa708bef6d5b896ca10dece0 |
|
10-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: Use the TargetSchedModel interface wherever possible.
Allows the new machine model to be used for NumMicroOps and OutputLatency.
Allows the HazardRecognizer to be disabled along with itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 714973e459d6611dd3e67f77968aba55528664b4 |
|
10-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: Remove LoopDependencies heuristic.
This wasn't contributing anything significant to postRA heuristics except compile time (by my measurements) and will be replaced by a more general heuristic for cross-region dependencies within the scheduler itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 39817f9d393fdc29ec35fc8626d8b372415df414 |
|
08-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: remove the unused getSpecialAddressLatency hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| a98f600a64b7b70754df58926ce8d60feeb9ce29 |
|
08-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: remove forceUnitLatencies. Defaults are handled by the default SchedModel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165417 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 781ab4777f683099b919597431022c77854ed415 |
|
18-Sep-2012 |
Andrew Trick <atrick@apple.com> |
misched: Make ScheduleDAGInstrs use the TargetSchedule interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164153 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| b720be6a50f4e1b3280d2b029ee38dda14577525 |
|
12-Sep-2012 |
Manman Ren <mren@apple.com> |
Release build: guard dump functions with
"#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)"
No functional change. Update r163339.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163653 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 77e300e8f0b8db8eec448cae9c87d7c5bfad9757 |
|
06-Sep-2012 |
Manman Ren <mren@apple.com> |
Release build: guard dump functions with "ifndef NDEBUG"
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| f036f7a1e79910bf5b5b6f37d2e512b4f01155a0 |
|
29-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Rename hasVolatileMemoryRef() to hasOrderedMemoryRef().
Ordered memory operations are more constrained than volatile loads and
stores because they must be ordered with respect to all other memory
operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162861 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| ffd2526fa4e2d78564694b4797b96236c9ba9d85 |
|
23-Aug-2012 |
Andrew Trick <atrick@apple.com> |
Simplify the computeOperandLatency API.
The logic for recomputing latency based on a ScheduleDAG edge was
shady. This bypasses the problem by requiring the client to provide
operand indices. This ensures consistent use of the machine model's
API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162420 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 8b5704f9589f20cdfb28b3632cc396995e4d8c45 |
|
31-Jul-2012 |
Andrew Trick <atrick@apple.com> |
Use the latest MachineRegisterInfo APIs. No functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 4b72ada1f4c1c90ead331a650956e7b14450080e |
|
28-Jul-2012 |
Andrew Trick <atrick@apple.com> |
Reenable a basic SSA DAG builder optimization.
Jakob fixed ProcessImplicifDefs in r159149.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160910 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 42120a2c5546f0eca9fdedf860b6a222e279971a |
|
14-Jun-2012 |
Andrew Trick <atrick@apple.com> |
misched: disable SSA check pending PR13112.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 1c2d3c538c6062655f2b37438cc69a769ab90942 |
|
13-Jun-2012 |
Andrew Trick <atrick@apple.com> |
sched: fix latency of memory dependence chain edges for consistency.
For store->load dependencies that may alias, we should always use
TrueMemOrderLatency, which may eventually become a subtarget hook. In
effect, we should guarantee at least TrueMemOrderLatency on at least
one DAG path from a store to a may-alias load.
This should fix the standard mode as well as -enable-aa-sched-mi".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158380 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| afc2657cc33988a178d3b21645dba54484600c5f |
|
06-Jun-2012 |
Andrew Trick <atrick@apple.com> |
Move RegisterPressure.h.
Make it a general utility for use by Targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| a7542d5f870c5d98960d1676e23ac1d1d975d7e5 |
|
06-Jun-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove unused private fields found by clang's new -Wunused-private-field.
There are some that I didn't remove this round because they looked like
obvious stubs. There are dead variables in gtest too, they should be
fixed upstream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| b7e0289fb320c8440ba5eed121a8b932dbd806a2 |
|
05-Jun-2012 |
Andrew Trick <atrick@apple.com> |
misched: API for minimum vs. expected latency.
Minimum latency determines per-cycle scheduling groups.
Expected latency determines critical path and cost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 396618b43a85e12d290a90b181c6af5d7c0c5f11 |
|
02-Jun-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch all register list clients to the new MC*Iterator interface.
No functional change intended.
Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.
This makes it possible to do so without changing all clients (again).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 93e29ce066c80528ab0afb90fdaabf734fb4b412 |
|
20-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use LiveRangeQuery in ScheduleDAGInstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| eb05b976e6e13fb0a8d1c45822dff67b0374e123 |
|
15-May-2012 |
Andrew Trick <atrick@apple.com> |
Add -enable-aa-sched-mi, off by default, for AliasAnalysis inside MachineScheduler.
This feature avoids creating edges in the scheduler's dependence graph
for non-aliasing memory operations according to whichever alias
analysis is available. It has been fully tested in Hexagon. Before
making this default, it needs to be extended to handle multiple
MachineMemOperands, compile time needs more evaluation, and
benchmarking on X86 and ARM is needed.
Patch by Sergei Larin!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| c3ad885dac8b4ed1a092e3276aeb84810a4a250c |
|
24-Apr-2012 |
Andrew Trick <atrick@apple.com> |
misched: DAG builder must special case earlyclobber
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 006e1abf76148626fb38de1b643c2d31de7f08a7 |
|
24-Apr-2012 |
Andrew Trick <atrick@apple.com> |
misched: DAG builder support for tracking register pressure within the current scheduling region.
The DAG builder is a convenient place to do it. Hopefully this is more
efficient than a separate traversal over the same region.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155456 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| a30444a69c2503ab7dae4c9d696fd3ade33e921d |
|
20-Apr-2012 |
Andrew Trick <atrick@apple.com> |
New and improved comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155229 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| c0ccb8bb17028fe0dda139c0972c0125d10e6053 |
|
20-Apr-2012 |
Andrew Trick <atrick@apple.com> |
SparseSet: Add support for key-derived indexes and arbitrary key types.
This nicely handles the most common case of virtual register sets, but
also handles anticipated cases where we will map pointers to IDs.
The goal is not to develop a completely generic SparseSet
template. Instead we want to handle the expected uses within llvm
without any template antics in the client code. I'm adding a bit of
template nastiness here, and some assumption about expected usage in
order to make the client code very clean.
The expected common uses cases I'm designing for:
- integer keys that need to be reindexed, and may map to additional
data
- densely numbered objects where we want pointer keys because no
number->object map exists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155227 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 918f38ab2420bbdc350a6ec8c6ba6b09e37126b2 |
|
20-Apr-2012 |
Andrew Trick <atrick@apple.com> |
misched: initialize BB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 007079201276368736fc893d4d5ec7aeeca00823 |
|
14-Apr-2012 |
Andrew Trick <atrick@apple.com> |
misched: Added CanHandleTerminators.
This is a special flag for targets that really want their block
terminators in the DAG. The default scheduler cannot handle this
correctly, so it becomes the specialized scheduler's responsibility to
schedule terminators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| a82d526b31cd9825684fdee5c3372bf55dad4f57 |
|
16-Mar-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
ScheduleDAGInstrs: When adding uses we add them into a set that's empty at the beginning, no need to maintain another set for the added regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152934 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| d3a7486ef351697450cfe87b6cce82a3eb906874 |
|
16-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched: add DAG edges from vreg defs to ExitSU.
These edges are not really necessary, but it is consistent with the
way we currently create physreg edges. Scheduler heuristics that
expect a DAG edge to the block terminator could benefit from this
change. Although in the future I hope we have a better mechanism for
modeling latency across scheduling regions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152895 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 17d35e57a585e869dc3084666abd17f173723735 |
|
14-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched: implemented a framework for top-down or bottom-up scheduling.
New flags: -misched-topdown, -misched-bottomup. They can be used with
the default scheduler or with -misched=shuffle. Without either
topdown/bottomup flag -misched=shuffle now alternates scheduling
direction.
LiveIntervals update is unimplemented with bottom-up scheduling, so
only -misched-topdown currently works.
Capped the ScheduleDAG hierarchy with a concrete ScheduleDAGMI class.
ScheduleDAGMI is aware of the top and bottom of the unscheduled zone
within the current region. Scheduling policy can be plugged into
the ScheduleDAGMI driver by implementing MachineSchedStrategy.
ConvergingScheduler is now the default scheduling algorithm.
It exercises the new driver but still does no reordering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152700 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 68675c6c5b173021807e4e12cd250eeba63f6d0d |
|
09-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched interface: rename Begin/End to RegionBegin/RegionEnd since they are not private.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152382 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| ed395c8c475692f5a43eb4b5c5562503d67616d0 |
|
08-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched prep: Expose the ScheduleDAGInstrs interface so targets may
implement their own MachineScheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152261 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| d790cada339d7af81650084b9bb6b2ad65566fbb |
|
08-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched prep: Comment the ScheduleDAGInstrs interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 035ec40eaf1dcd8f4809fb183098259f2dec75b9 |
|
08-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched prep: Cleanup ScheduleDAGInstrs interface.
ScheduleDAGInstrs will be the main interface for MI-level
schedulers. Make sure it's readable: one page of protected fields, one
page of public methids.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152258 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| cf46b5acfd6e0ab5d21ec3160cec195d0eb77b0b |
|
08-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched prep: rename InsertPos to End.
ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152256 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 953be893e8cffa0ef9bf410036cd96aeb526e98a |
|
08-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched preparation: rename core scheduler methods for consistency.
We had half the API with one convention, half with another. Now was a
good time to clean it up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 47c144505b9be28ed22c626b3a407c11dba2fec5 |
|
07-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.
ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation.
ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class.
ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target.
Specific changes:
- Removed driver code from ScheduleDAG. clearDAG is the only interface needed.
- Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls.
- Added ScheduleDAGInstrs::begin()/end() public API.
- Moved Sequence into the driver layer, which is specific to the scheduling algorithm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152208 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 84b454d1a270a5d685e01686ed15e68c44b0b56a |
|
07-Mar-2012 |
Andrew Trick <atrick@apple.com> |
misched preparation: modularize schedule emission.
ScheduleDAG has nothing to do with how the instructions are scheduled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152206 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 56b94c52c9bf0342106ca7d274b9bb469d5ef619 |
|
07-Mar-2012 |
Andrew Trick <atrick@apple.com> |
Cleanup in preparation for misched: Move DAG visualization logic.
Soon, ScheduleDAG will not refer to the BB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| e4fd907e72a599eddfa7a81eac4366b5b82523e3 |
|
04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store register overlaps to reduce static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 702d489a959b202ab06ce4bafa0bcb1fbfd2c3e4 |
|
24-Feb-2012 |
Andrew Trick <atrick@apple.com> |
PostRA sched: speed up physreg tracking by not abusing SparseSet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151348 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 63d578b5aa0f07a0789d3bae84750ea145ec06b1 |
|
23-Feb-2012 |
Andrew Trick <atrick@apple.com> |
misched: cleanup reaching def computation
Ignore undef uses completely.
Use a more explicit SlotIndex API.
Add more explicit comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151233 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 81a682a4c004b0f44452ef824637a1b6face178f |
|
23-Feb-2012 |
Andrew Trick <atrick@apple.com> |
PostRASched: Convert physreg def/use tracking to Jakob's SparseSet.
Added array subscript to SparseSet for convenience.
Slight reorg to make it easier to manage the def/use sets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 02634be4d4c8a72b652ae3e76b327a12593b03d4 |
|
22-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't compute latencies for regmask operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151211 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 8ae3ac7a8c2112ab739b4a0dc24f28b2bbb84117 |
|
22-Feb-2012 |
Andrew Trick <atrick@apple.com> |
misched: Use SparseSet for VRegDegs for constant time clear().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151205 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 2fc0977a988a49dacb0ca0954e40ddc4e8849d4c |
|
22-Feb-2012 |
Andrew Trick <atrick@apple.com> |
Comment from code review
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151178 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| cc77b54036cfaaab9e0d9f2c731efbd2b7753cc9 |
|
22-Feb-2012 |
Andrew Trick <atrick@apple.com> |
misched: DAG builder should not track dependencies for SSA defs.
The vast majority of virtual register definitions don't need an entry
in the DAG builder's VRegDefs set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| b4566a999970b514d7c6973d99e293a6625d3f70 |
|
22-Feb-2012 |
Andrew Trick <atrick@apple.com> |
Initialize SUnits before DAG building.
Affect on SD scheduling and postRA scheduling:
Printing the DAG will display the nodes in top-down topological order.
This matches the order within the MBB and makes my life much easier in general.
Affect on misched:
We don't need to track virtual register uses at all. This is awesome.
I also intend to rely on the SUnit ID as a topo-sort index. So if A < B then we cannot have an edge B -> A.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151135 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 19273aec441411b4d571fdb87c6daa0fbe7a33a0 |
|
21-Feb-2012 |
Andrew Trick <atrick@apple.com> |
Clear virtual registers after they are no longer referenced.
Passes after RegAlloc should be able to rely on MRI->getNumVirtRegs() == 0.
This makes sharing code for pre/postRA passes more robust.
Now, to check if a pass is running before the RA pipeline begins, use MRI->isSSA().
To check if a pass is running after the RA pipeline ends, use !MRI->getNumVirtRegs().
PEI resets virtual regs when it's done scavenging.
PTX will either have to provide its own PEI pass or assign physregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151032 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 3c58ba8ea7ec097d69d7f7be5930a4a4d7405a18 |
|
14-Jan-2012 |
Andrew Trick <atrick@apple.com> |
misched: Initial code for building an MI level scheduling DAG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148174 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 7ebcaf4cf929ef041ae6c9c07b897e4d0aa8ad06 |
|
14-Jan-2012 |
Andrew Trick <atrick@apple.com> |
Move physreg dependency generation into aptly named addPhysRegDeps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148173 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 5e920d7c83c20474fc3470209869978628ccf8da |
|
14-Jan-2012 |
Andrew Trick <atrick@apple.com> |
misched: Added ScheduleDAGInstrs::IsPostRA
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148172 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 977679d6034791fd48a344e5b990503ba50fc242 |
|
07-Jan-2012 |
Evan Cheng <evan.cheng@apple.com> |
Added a late machine instruction copy propagation pass. This catches
opportunities that only present themselves after late optimizations
such as tail duplication .e.g.
## BB#1:
movl %eax, %ecx
movl %ecx, %eax
ret
The register allocator also leaves some of them around (due to false
dep between copies from phi-elimination, etc.)
This required some changes in codegen passes. Post-ra scheduler and the
pseudo-instruction expansion passes have been moved after branch folding
and tail merging. They were before branch folding before because it did
not always update block livein's. That's fixed now. The pass change makes
independently since we want to properly schedule instructions after
branch folding / tail duplication.
rdar://10428165
rdar://10640363
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147716 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| fcb0a278951d5e6bd878e183f2f1e9b3abf2e200 |
|
05-Jan-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Remove an unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147605 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 877ae2ee17cb89c57310c65fb4046e49020a0b55 |
|
05-Jan-2012 |
Andrew Trick <atrick@apple.com> |
Minor postra scheduler cleanup. It could result in more precise antidependence latency on ARM in exceedingly rare cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 020f4106f820648fd7e91956859844a80de13974 |
|
14-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Model ARM predicated write as read-mod-write. e.g.
r0 = mov #0
r0 = moveq #1
Then the second instruction has an implicit data dependency on the first
instruction. Sadly I have yet to come up with a small test case that
demonstrate the post-ra scheduler taking advantage of this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146583 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 12dfdb424ddcfabb347f168f9332795ba443ccd3 |
|
14-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Allow target to specify register output dependency. Still default to one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146547 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| ddfd1377d2e4154d44dc3ad217735adc15af2e3f |
|
14-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 5a96b3dad2f634c9081c8b2b6c2575441dc5a2bd |
|
07-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 7c2a4a30e0e16762c75adacebd05ec9fcbccf16b |
|
06-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
First chunk of MachineInstr bundle support.
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| db809e0eb7055a5247c80500fe0ba0ac22199722 |
|
02-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
make sure ScheduleDAGInstrs::EmitSchedule does not crash when the first instruction in Sequence is a Noop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145677 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| e8deca83c157999062b4894163fd6b5023c5cf91 |
|
07-Oct-2011 |
Andrew Trick <atrick@apple.com> |
PostRA scheduler fix. Clear stale loop dependencies.
Fixes <rdar://problem/10235725>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141357 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 4563bbaba7fad4403acf0236cbd75805c68f2a90 |
|
07-Oct-2011 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141356 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 5b1b4489cf3a0f56f8be0673fc5cc380a32d277b |
|
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetSubtarget to TargetSubtargetInfo for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| ab8be96fd30ca9396e6b84fdddf1ac6208984cad |
|
29-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134049 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| e837dead3c8dc3445ef6a0e2322179c57e264a13 |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| ee1f87881b185873b1e285a2395a2c6a97c47ec4 |
|
02-Jun-2011 |
Devang Patel <dpatel@apple.com> |
Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| e29e8e100ea38be1771e5f010a5511cbb990d515 |
|
02-Jun-2011 |
Devang Patel <dpatel@apple.com> |
Update DBG_VALUEs while breaking anti dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132487 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| cf4cc84738abc5f63a05b0956e756c66c519ded5 |
|
02-Jun-2011 |
Devang Patel <dpatel@apple.com> |
During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def.
Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132483 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 9b668535a8900a0a86dfa410e2ed843db4b5555e |
|
06-May-2011 |
Andrew Trick <atrick@apple.com> |
Added an assertion, and updated a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| ee1091589225d8de4cb8bc065bff9376bbe661eb |
|
05-May-2011 |
Andrew Trick <atrick@apple.com> |
ARM post RA scheduler compile time fix.
BuildSchedGraph was quadratic in the number of calls in the basic
block. After this fix, it keeps only a single call at the top of the
DefList so compile time doesn't blow up on large blocks. This reduces
postRA sched time on an external test case from 81s to 0.3s. Although
r130800 (reduced ARM register alias defs) also partially fixes the
issue by reducing the constant overhead of checking call interference
by an order of magnitude.
Fixes <rdar://problem/7662664> very poor compile time with post RA scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| f405b1ad19940ddd0b66ec0761e636b953af2c2e |
|
05-May-2011 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 7a2bdde0a0eebcd2125055e0eacaca040f0b766c |
|
15-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| c36b7069b42bece963b7e6adf020353ce990ef76 |
|
08-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Do not model all INLINEASM instructions as having unmodelled side effects.
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check
the operand when the instruction is an INLINEASM.
This allows memory instructions to be moved around INLINEASM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 5034dd318a9dfa0dc45a3ac01e58e60f2aa2498d |
|
15-Dec-2010 |
Dan Gohman <gohman@apple.com> |
Move Value::getUnderlyingObject to be a standalone
function so that it can live in Analysis instead of
VMCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 8239daf7c83a65a189c352cce3191cdc3bbfe151 |
|
03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Two sets of changes. Sorry they are intermingled.
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
"optimize for latency". Call instructions don't have the right latency and
this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
not # of micro-ops since multi-latency instructions is completely executed
even when the predicate is false. Also, some instruction will be "slower"
when they are predicated due to the register def becoming implicit input.
rdar://8598427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| de5fa932b9bc0eebe803c9549586bf512eeb12f9 |
|
28-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Putting r117193 back except for the compile time cost. Rather than assuming fallthroughs uses all registers, just gather the union of all successor liveins.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 38fd9f2a2dedc2c4ce73fcf4890b79b6eb8c2e8f |
|
26-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Neuter r117193 as it causes significant post-ra scheduler compile time regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117329 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| ec6906ba47d6d32cc817e85eddb87b320d6ae18c |
|
23-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Properly model the latency of register defs which are 1) function returns or
2) live-outs.
Previously the post-RA schedulers completely ignore these dependencies since
returns, branches, etc. are all scheduling barriers. This patch model the
latencies between instructions being scheduled and the barriers. It also
handle calls by marking their register uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| d82de8341c99c1756624020000bd51a03a5f355c |
|
09-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Avoid compiler warning: comparison between signed and unsigned integer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 1aca5bc1353d4e2c7706149efbc5393aa9e2cc3f |
|
08-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix operand latency computation in cases where the definition operand is
implicit. e.g.
%D6<def>, %D7<def> = VLD1q16 %R2<kill>, 0, ..., %Q3<imp-def>
%Q1<def> = VMULv8i16 %Q1<kill>, %Q3<kill>, ...
The real definition indices are 0,1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116080 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 9c220fc165ab3543a383d7101cb80544e0c220e3 |
|
06-Oct-2010 |
Nick Lewycky <nicholas@mxc.ca> |
Remove unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| a0792de66c8364d47b0a688c7f408efb7b10f31b |
|
06-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 3881cb7a5d54c0011b40997adcd742e1c7b91abd |
|
30-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP
pipeline forwarding path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115098 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 3ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1 |
|
10-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| f28dd8861190df4926cdc66201a39a6af950d564 |
|
24-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change ScheduleDAGInstrs::Defs and ::Uses to be variable-size vectors
instead of fixed size arrays, so that increasing FirstVirtualRegister to 16K
won't cause a compile time performance regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109330 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 87ea294b0d72ef5f29c6d3ea9c9c5faa8be7abc4 |
|
15-Jul-2010 |
Bill Wendling <isanbard@gmail.com> |
Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108452 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 309d20c89c5fde5a6ebe3b40a3fd0fbc3e5ffe40 |
|
20-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix the post-RA instruction scheduler to handle instructions referenced by
more than one dbg_value instruction. rdar://7759363
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104174 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| af1d8ca44a18f304f207e209b3bdb94b590f86ff |
|
01-May-2010 |
Dan Gohman <gohman@apple.com> |
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 3fb150a9024a38872ec4abbc3300e08a8bfc1812 |
|
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Fix -Wcast-qual warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| a69ec09364213311f1ced39271a30f39076b207e |
|
22-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Reduce indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| fc91114a2e622776d003d121eebc3c1b79f418f3 |
|
22-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99195 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33 |
|
10-Mar-2010 |
Dale Johannesen <dalej@apple.com> |
Progress towards shepherding debug info through SelectionDAG.
No functional effect yet. This is still evolving and should
not be viewed as final.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98195 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 1df9859c40492511b8aa4321eb76496005d3b75b |
|
16-Feb-2010 |
Duncan Sands <baldrick@free.fr> |
There are two ways of checking for a given type, for example isa<PointerType>(T)
and T->isPointerTy(). Convert most instances of the first form to the second form.
Requested by Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96344 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 980d494ab6ba3c812194f5cbc14992fa35dcc976 |
|
09-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix dependencies added to model memory aliasing for post-RA scheduling. The dependencies were overly conservative for memory access that are known not to alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 5be870add97c52862285eddaf950c806a3fa076b |
|
05-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Correctly add chain dependencies around calls and unknown-side-effect instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86080 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| a9e610768bad77f400bc763a0011e77aee19053e |
|
03-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
<rdar://problem/7352605>. When building schedule graph use mayAlias information to avoid chaining loads/stores of spill slots with non-aliased memory ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85934 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 7c9b1ac5073a4988a9ed39aed6cd5a22e6a1c24f |
|
02-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Chain dependencies used to enforce memory order should have latency of 0 (except for true dependency of Store followed by aliased Load... we estimate that case with a single cycle of latency assuming the hardware will bypass)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85807 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 91203cf87b8a72227c78a9eeae8bb744dfcc4ef0 |
|
26-Oct-2009 |
Dan Gohman <gohman@apple.com> |
When checking whether a def of an aliased register is dead, ask the
machineinstr whether the aliased register is dead, rather than the original
register is dead. This allows it to get the correct answer when examining
an instruction like this:
CALLpcrel32 <ga:foo>, %AL<imp-def>, %EAX<imp-def,dead>
where EAX is dead but a subregister of it is still live. This fixes PR5294.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85135 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 38bdfc69cbe370ce5f623df4449afa32cda97422 |
|
18-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Spill slots cannot alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84432 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| ff89dcb06fbd103373436e2d0ae85f252fae2254 |
|
18-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2.
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| a70dca156fa76d452f54829b5c5f962ddfd94ef2 |
|
10-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Factor out LiveIntervalAnalysis' code to determine whether an instruction
is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.
This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| e33f44cfc547359bc28526e4c5e1852b600b4448 |
|
07-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Replace TargetInstrInfo::isInvariantLoad and its target-specific
implementations with a new MachineInstr::isInvariantLoad, which uses
MachineMemOperands and is target-independent. This brings MachineLICM
and other functionality to targets which previously lacked an
isInvariantLoad implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83475 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| c76909abfec876c6b751d693ebd3df07df686aa0 |
|
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
This eliminates MachineInstr's std::list member and allows the data to be
created by isel and live for the remainder of codegen, avoiding a lot of
copying and unnecessary translation. This also shrinks MemSDNode.
- Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
fields for MachineMemOperands.
- Change MemSDNode to have a MachineMemOperand member instead of its own
fields with the same information. This introduces some redundancy, but
it's more consistent with what MachineInstr will eventually want.
- Ignore alignment when searching for redundant loads for CSE, but remember
the greatest alignment.
Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| fb2e752e4175920d0531f2afc93a23d0cdf4db14 |
|
18-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| dc4bdcdef1c8dd1a28b82deb08df039e5c0ffc5a |
|
19-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Use the schedule itinerary operand use/def cycle information to adjust dependence edge latency for post-RA scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 710461688bba935f0ad5c75da7fec2ad0f225c00 |
|
13-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Add callback to allow target to adjust latency of schedule dependency edge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78910 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| d94a4e5d8de1145be200ff7223f98b0928462b94 |
|
10-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 748f98f90836dbb4c36fea67c9ebe7b6bb13255e |
|
07-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78362 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 8906f950068fab18a5d1065ec11bd6563a46728d |
|
17-Jul-2009 |
Dan Gohman <gohman@apple.com> |
Eliminate yet another copy of getOpcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76236 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 16a2c927e95c29a316d0271c93e0490ce3bc06ce |
|
14-Jul-2009 |
Dan Gohman <gohman@apple.com> |
Move isLCSSAForm, isLoopInvariant, getCanonicalInductionVariable,
and related functions out of LoopBase and into Loop, since they
are specific to BasicBlock-based loops. This also allows the code
to be moved out-of-line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75523 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 47ac0f0c7c39289f5970688154e385be22b7f293 |
|
11-Feb-2009 |
Dan Gohman <gohman@apple.com> |
When scheduling a block in parts, keep track of the overall
instruction index across each part. Instruction indices are used
to make live range queries, and live ranges can extend beyond
scheduling region boundaries.
Refactor the ScheduleDAGSDNodes class some more so that it
doesn't have to worry about this additional information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 9e64bbb322417c09f27afdf08e3946287c9df5aa |
|
11-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Factor out more code for computing register live-range informationfor
scheduling, and generalize is so that preserves state across
scheduling regions. This fixes incorrect live-range information around
terminators and labels, which are effective region boundaries.
In place of looking for terminators to anchor inter-block dependencies,
introduce special entry and exit scheduling units for this purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64254 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 6dc75fe5279e2c12bda13dcc4a1a13908de8596f |
|
06-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Move ScheduleDAGInstrs.h to be a private header. Front-ends
that used this header to select a scheduling policy should
use SchedulerRegistry.h instead (llvm-gcc and clang were
updated a while ago).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63934 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 3311a1f8f0d8a2c6d940802bbb95eba0b801a615 |
|
30-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Fix a post-RA scheduling dependency bug.
If a MachineInstr doesn't have a memoperand but has an opcode that
is known to load or store, assume its memory reference may alias
*anything*, including stack slots which the compiler completely
controls.
To partially compensate for this, teach the ScheduleDAG building
code to do basic getUnderlyingValue analysis. This greatly
reduces the number of instructions that require restrictive
dependencies. This code will need to be revisited when we start
doing real alias analysis, but it should suffice for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| f7119393a97c2a10757084b6bc186380f8c19a73 |
|
16-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Instead of adding dependence edges between terminator instructions
and every other instruction in their blocks to keep the terminator
instructions at the end, teach the post-RA scheduler how to operate
on ranges of instructions, and exclude terminators from the range
of instructions that get scheduled.
Also, exclude mid-block labels, such as EH_LABEL instructions, and
schedule code before them separately from code after them. This
fixes problems with the post-RA scheduler moving code past
EH_LABELs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 79ce276083ced01256a0eb7d80731e4948ca6e87 |
|
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.
To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 0b1d4a798d1dd2f39521b6b381cd1c1911c9ab52 |
|
23-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Clean up the atomic opcodes in SelectionDAG.
This removes all the _8, _16, _32, and _64 opcodes and replaces each
group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode
is now used to carry the size information. In tablegen, the size-specific
opcodes are replaced by size-independent opcodes that utilize the
ability to compose them with predicates.
This shrinks the per-opcode tables and makes the code that handles
atomics much more concise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61389 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| c9a5b9e38b442c2ae6b115213a07df3fcd14708d |
|
23-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Rename BuildSchedUnits to BuildSchedGraph, and refactor the
code in ScheduleDAGSDNodes' BuildSchedGraph into separate functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61376 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 237dee125997dcaf16e391878465162cc680c0fa |
|
23-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Use isTerminator() instead of isBranch()||isReturn() in
several places. isTerminator() returns true for a superset
of cases, and includes things like FP_REG_KILL, which are
nither return or branch but aren't safe to move/remat/etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61373 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 8749b61178228ba1fb2668034d79da1b247173d7 |
|
16-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Add initial support for back-scheduling address computations,
especially in the case of addresses computed from loop induction
variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61075 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 3f23744df4809eba94284e601e81489212c974d4 |
|
16-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Fix some register-alias-related bugs in the post-RA scheduler liveness
computation code. Also, avoid adding output-depenency edges when both
defs are dead, which frequently happens with EFLAGS defs.
Compute Depth and Height lazily, and always in terms of edge latency
values. For the schedulers that don't care about latency, edge latencies
are set to 1.
Eliminate Cycle and CycleBound, and LatencyPriorityQueue's Latencies array.
These are all subsumed by the Depth and Height fields.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 4ea8e85e19b844ef0ff704f27959b6a2ea7369f9 |
|
16-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Add a simple target-independent heuristic to allow targets with no
instruction itinerary data to back-schedule loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61070 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 54e4c36a7349e94a84773afb56eccd4ca65b49e9 |
|
09-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Rewrite the SDep class, and simplify some of the related code.
The Cost field is removed. It was only being used in a very limited way,
to indicate when the scheduler should attempt to protect a live register,
and it isn't really needed to do that. If we ever want the scheduler to
start inserting copies in non-prohibitive situations, we'll have to
rethink some things anyway.
A Latency field is added. Instead of giving each node a single
fixed latency, each edge can have its own latency. This will eventually
be used to model various micro-architecture properties more accurately.
The PointerIntPair class and an internal union are now used, which
reduce the overall size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60806 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| a629b48a668c778e0cb951c7eb2b47bda0c922f0 |
|
08-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Fix the top-level comments, and fix some 80-column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60707 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 6a9041e5ca9bdf2c1b586a7b2c6488374b39be74 |
|
04-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Add minimal support for disambiguating memory references. Currently
the main thing this covers is spills to distinct spill slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 974b5f53f70294d6fb586c7a47fee505b3eaf1ae |
|
24-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Pass the isAntiDep argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59968 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 37d8b3193d6584356c2bfc53f0d44701ffd48f5e |
|
21-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Correctly set the isCtrl flag for chain dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59837 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| fc626b62b877beec1cc3c0289eb794f28614e23f |
|
21-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Update comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59836 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| f6b7a47d5d6e2703591b95b10b2c5be5b5fd09cd |
|
21-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Set the isAntiDep flag in the MachineInstr scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59787 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
|
| 787782f4ca0cca2523825131c24a6f78535a3eb8 |
|
21-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Use ComputeLatency in the MachineInstr scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59777 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
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| c8c2827993204207ca70a93f62f233fbe81b97ef |
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21-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Implement ComputeLatency for MachineInstr ScheduleDAGs. Factor
some of the latency computation logic out of the SDNode
ScheduleDAG code into a TargetInstrItineraries helper method
to help with this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59761 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
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| 8eaf41de8adb764b16712485a385afab8b83f1ca |
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20-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Treat mid-block labels the same as terminators when building the
MachineInstr scheduling DAG, meaning they implicitly depend on all
preceding defs. This fixes Benchmarks/Shootout-C++/except and
Regression/C++/EH/simple_rethrow in
-relocation-model=pic -disable-post-RA-scheduler=false
mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59747 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
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| 343f0c046702831a4a6aec951b6a297a23241a55 |
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20-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Experimental post-pass scheduling support. Post-pass scheduling
is currently off by default, and can be enabled with
-disable-post-RA-scheduler=false.
This doesn't have a significant impact on most code yet because it doesn't
yet do anything to address anti-dependencies and it doesn't attempt to
disambiguate memory references. Also, several popular targets
don't have pipeline descriptions yet.
The majority of the changes here are splitting the SelectionDAG-specific
code out of ScheduleDAG, so that ScheduleDAG can be moved to
libLLVMCodeGen.a. The interface between ScheduleDAG-using code and
the rest of the scheduling code is somewhat rough and will evolve.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
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