ScheduleDAGInstrs.cpp revision 738073c4aa474e27c9d3c991daf593bddce54718
1//===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the ScheduleDAGInstrs class, which implements re-scheduling 11// of MachineInstrs. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "misched" 16#include "llvm/CodeGen/ScheduleDAGInstrs.h" 17#include "llvm/ADT/MapVector.h" 18#include "llvm/ADT/SmallPtrSet.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ValueTracking.h" 22#include "llvm/CodeGen/LiveIntervalAnalysis.h" 23#include "llvm/CodeGen/MachineFunctionPass.h" 24#include "llvm/CodeGen/MachineMemOperand.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/CodeGen/RegisterPressure.h" 28#include "llvm/CodeGen/ScheduleDFS.h" 29#include "llvm/IR/Operator.h" 30#include "llvm/MC/MCInstrItineraries.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/Support/Format.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/TargetInstrInfo.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetRegisterInfo.h" 38#include "llvm/Target/TargetSubtargetInfo.h" 39#include <queue> 40 41using namespace llvm; 42 43static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden, 44 cl::ZeroOrMore, cl::init(false), 45 cl::desc("Enable use of AA during MI GAD construction")); 46 47ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf, 48 const MachineLoopInfo &mli, 49 const MachineDominatorTree &mdt, 50 bool IsPostRAFlag, 51 LiveIntervals *lis) 52 : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), LIS(lis), 53 IsPostRA(IsPostRAFlag), CanHandleTerminators(false), FirstDbgValue(0) { 54 assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals"); 55 DbgValues.clear(); 56 assert(!(IsPostRA && MRI.getNumVirtRegs()) && 57 "Virtual registers must be removed prior to PostRA scheduling"); 58 59 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>(); 60 SchedModel.init(*ST.getSchedModel(), &ST, TII); 61} 62 63/// getUnderlyingObjectFromInt - This is the function that does the work of 64/// looking through basic ptrtoint+arithmetic+inttoptr sequences. 65static const Value *getUnderlyingObjectFromInt(const Value *V) { 66 do { 67 if (const Operator *U = dyn_cast<Operator>(V)) { 68 // If we find a ptrtoint, we can transfer control back to the 69 // regular getUnderlyingObjectFromInt. 70 if (U->getOpcode() == Instruction::PtrToInt) 71 return U->getOperand(0); 72 // If we find an add of a constant, a multiplied value, or a phi, it's 73 // likely that the other operand will lead us to the base 74 // object. We don't have to worry about the case where the 75 // object address is somehow being computed by the multiply, 76 // because our callers only care when the result is an 77 // identifiable object. 78 if (U->getOpcode() != Instruction::Add || 79 (!isa<ConstantInt>(U->getOperand(1)) && 80 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul && 81 !isa<PHINode>(U->getOperand(1)))) 82 return V; 83 V = U->getOperand(0); 84 } else { 85 return V; 86 } 87 assert(V->getType()->isIntegerTy() && "Unexpected operand type!"); 88 } while (1); 89} 90 91/// getUnderlyingObjects - This is a wrapper around GetUnderlyingObjects 92/// and adds support for basic ptrtoint+arithmetic+inttoptr sequences. 93static void getUnderlyingObjects(const Value *V, 94 SmallVectorImpl<Value *> &Objects) { 95 SmallPtrSet<const Value*, 16> Visited; 96 SmallVector<const Value *, 4> Working(1, V); 97 do { 98 V = Working.pop_back_val(); 99 100 SmallVector<Value *, 4> Objs; 101 GetUnderlyingObjects(const_cast<Value *>(V), Objs); 102 103 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), IE = Objs.end(); 104 I != IE; ++I) { 105 V = *I; 106 if (!Visited.insert(V)) 107 continue; 108 if (Operator::getOpcode(V) == Instruction::IntToPtr) { 109 const Value *O = 110 getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0)); 111 if (O->getType()->isPointerTy()) { 112 Working.push_back(O); 113 continue; 114 } 115 } 116 Objects.push_back(const_cast<Value *>(V)); 117 } 118 } while (!Working.empty()); 119} 120 121typedef SmallVector<PointerIntPair<const Value *, 1, bool>, 4> 122UnderlyingObjectsVector; 123 124/// getUnderlyingObjectsForInstr - If this machine instr has memory reference 125/// information and it can be tracked to a normal reference to a known 126/// object, return the Value for that object. 127static void getUnderlyingObjectsForInstr(const MachineInstr *MI, 128 const MachineFrameInfo *MFI, 129 UnderlyingObjectsVector &Objects) { 130 if (!MI->hasOneMemOperand() || 131 !(*MI->memoperands_begin())->getValue() || 132 (*MI->memoperands_begin())->isVolatile()) 133 return; 134 135 const Value *V = (*MI->memoperands_begin())->getValue(); 136 if (!V) 137 return; 138 139 SmallVector<Value *, 4> Objs; 140 getUnderlyingObjects(V, Objs); 141 142 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), IE = Objs.end(); 143 I != IE; ++I) { 144 bool MayAlias = true; 145 V = *I; 146 147 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) { 148 // For now, ignore PseudoSourceValues which may alias LLVM IR values 149 // because the code that uses this function has no way to cope with 150 // such aliases. 151 152 if (PSV->isAliased(MFI)) { 153 Objects.clear(); 154 return; 155 } 156 157 MayAlias = PSV->mayAlias(MFI); 158 } else if (!isIdentifiedObject(V)) { 159 Objects.clear(); 160 return; 161 } 162 163 Objects.push_back(UnderlyingObjectsVector::value_type(V, MayAlias)); 164 } 165} 166 167void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) { 168 BB = bb; 169} 170 171void ScheduleDAGInstrs::finishBlock() { 172 // Subclasses should no longer refer to the old block. 173 BB = 0; 174} 175 176/// Initialize the DAG and common scheduler state for the current scheduling 177/// region. This does not actually create the DAG, only clears it. The 178/// scheduling driver may call BuildSchedGraph multiple times per scheduling 179/// region. 180void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb, 181 MachineBasicBlock::iterator begin, 182 MachineBasicBlock::iterator end, 183 unsigned regioninstrs) { 184 assert(bb == BB && "startBlock should set BB"); 185 RegionBegin = begin; 186 RegionEnd = end; 187 NumRegionInstrs = regioninstrs; 188 MISUnitMap.clear(); 189 190 ScheduleDAG::clearDAG(); 191} 192 193/// Close the current scheduling region. Don't clear any state in case the 194/// driver wants to refer to the previous scheduling region. 195void ScheduleDAGInstrs::exitRegion() { 196 // Nothing to do. 197} 198 199/// addSchedBarrierDeps - Add dependencies from instructions in the current 200/// list of instructions being scheduled to scheduling barrier by adding 201/// the exit SU to the register defs and use list. This is because we want to 202/// make sure instructions which define registers that are either used by 203/// the terminator or are live-out are properly scheduled. This is 204/// especially important when the definition latency of the return value(s) 205/// are too high to be hidden by the branch or when the liveout registers 206/// used by instructions in the fallthrough block. 207void ScheduleDAGInstrs::addSchedBarrierDeps() { 208 MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : 0; 209 ExitSU.setInstr(ExitMI); 210 bool AllDepKnown = ExitMI && 211 (ExitMI->isCall() || ExitMI->isBarrier()); 212 if (ExitMI && AllDepKnown) { 213 // If it's a call or a barrier, add dependencies on the defs and uses of 214 // instruction. 215 for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) { 216 const MachineOperand &MO = ExitMI->getOperand(i); 217 if (!MO.isReg() || MO.isDef()) continue; 218 unsigned Reg = MO.getReg(); 219 if (Reg == 0) continue; 220 221 if (TRI->isPhysicalRegister(Reg)) 222 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg)); 223 else { 224 assert(!IsPostRA && "Virtual register encountered after regalloc."); 225 if (MO.readsReg()) // ignore undef operands 226 addVRegUseDeps(&ExitSU, i); 227 } 228 } 229 } else { 230 // For others, e.g. fallthrough, conditional branch, assume the exit 231 // uses all the registers that are livein to the successor blocks. 232 assert(Uses.empty() && "Uses in set before adding deps?"); 233 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), 234 SE = BB->succ_end(); SI != SE; ++SI) 235 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(), 236 E = (*SI)->livein_end(); I != E; ++I) { 237 unsigned Reg = *I; 238 if (!Uses.contains(Reg)) 239 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg)); 240 } 241 } 242} 243 244/// MO is an operand of SU's instruction that defines a physical register. Add 245/// data dependencies from SU to any uses of the physical register. 246void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { 247 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); 248 assert(MO.isDef() && "expect physreg def"); 249 250 // Ask the target if address-backscheduling is desirable, and if so how much. 251 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>(); 252 253 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true); 254 Alias.isValid(); ++Alias) { 255 if (!Uses.contains(*Alias)) 256 continue; 257 for (Reg2SUnitsMap::iterator I = Uses.find(*Alias); I != Uses.end(); ++I) { 258 SUnit *UseSU = I->SU; 259 if (UseSU == SU) 260 continue; 261 262 // Adjust the dependence latency using operand def/use information, 263 // then allow the target to perform its own adjustments. 264 int UseOp = I->OpIdx; 265 MachineInstr *RegUse = 0; 266 SDep Dep; 267 if (UseOp < 0) 268 Dep = SDep(SU, SDep::Artificial); 269 else { 270 // Set the hasPhysRegDefs only for physreg defs that have a use within 271 // the scheduling region. 272 SU->hasPhysRegDefs = true; 273 Dep = SDep(SU, SDep::Data, *Alias); 274 RegUse = UseSU->getInstr(); 275 } 276 Dep.setLatency( 277 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse, 278 UseOp)); 279 280 ST.adjustSchedDependency(SU, UseSU, Dep); 281 UseSU->addPred(Dep); 282 } 283 } 284} 285 286/// addPhysRegDeps - Add register dependencies (data, anti, and output) from 287/// this SUnit to following instructions in the same scheduling region that 288/// depend the physical register referenced at OperIdx. 289void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) { 290 const MachineInstr *MI = SU->getInstr(); 291 const MachineOperand &MO = MI->getOperand(OperIdx); 292 293 // Optionally add output and anti dependencies. For anti 294 // dependencies we use a latency of 0 because for a multi-issue 295 // target we want to allow the defining instruction to issue 296 // in the same cycle as the using instruction. 297 // TODO: Using a latency of 1 here for output dependencies assumes 298 // there's no cost for reusing registers. 299 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output; 300 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true); 301 Alias.isValid(); ++Alias) { 302 if (!Defs.contains(*Alias)) 303 continue; 304 for (Reg2SUnitsMap::iterator I = Defs.find(*Alias); I != Defs.end(); ++I) { 305 SUnit *DefSU = I->SU; 306 if (DefSU == &ExitSU) 307 continue; 308 if (DefSU != SU && 309 (Kind != SDep::Output || !MO.isDead() || 310 !DefSU->getInstr()->registerDefIsDead(*Alias))) { 311 if (Kind == SDep::Anti) 312 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias)); 313 else { 314 SDep Dep(SU, Kind, /*Reg=*/*Alias); 315 Dep.setLatency( 316 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); 317 DefSU->addPred(Dep); 318 } 319 } 320 } 321 } 322 323 if (!MO.isDef()) { 324 SU->hasPhysRegUses = true; 325 // Either insert a new Reg2SUnits entry with an empty SUnits list, or 326 // retrieve the existing SUnits list for this register's uses. 327 // Push this SUnit on the use list. 328 Uses.insert(PhysRegSUOper(SU, OperIdx, MO.getReg())); 329 } 330 else { 331 addPhysRegDataDeps(SU, OperIdx); 332 unsigned Reg = MO.getReg(); 333 334 // clear this register's use list 335 if (Uses.contains(Reg)) 336 Uses.eraseAll(Reg); 337 338 if (!MO.isDead()) { 339 Defs.eraseAll(Reg); 340 } else if (SU->isCall) { 341 // Calls will not be reordered because of chain dependencies (see 342 // below). Since call operands are dead, calls may continue to be added 343 // to the DefList making dependence checking quadratic in the size of 344 // the block. Instead, we leave only one call at the back of the 345 // DefList. 346 Reg2SUnitsMap::RangePair P = Defs.equal_range(Reg); 347 Reg2SUnitsMap::iterator B = P.first; 348 Reg2SUnitsMap::iterator I = P.second; 349 for (bool isBegin = I == B; !isBegin; /* empty */) { 350 isBegin = (--I) == B; 351 if (!I->SU->isCall) 352 break; 353 I = Defs.erase(I); 354 } 355 } 356 357 // Defs are pushed in the order they are visited and never reordered. 358 Defs.insert(PhysRegSUOper(SU, OperIdx, Reg)); 359 } 360} 361 362/// addVRegDefDeps - Add register output and data dependencies from this SUnit 363/// to instructions that occur later in the same scheduling region if they read 364/// from or write to the virtual register defined at OperIdx. 365/// 366/// TODO: Hoist loop induction variable increments. This has to be 367/// reevaluated. Generally, IV scheduling should be done before coalescing. 368void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) { 369 const MachineInstr *MI = SU->getInstr(); 370 unsigned Reg = MI->getOperand(OperIdx).getReg(); 371 372 // Singly defined vregs do not have output/anti dependencies. 373 // The current operand is a def, so we have at least one. 374 // Check here if there are any others... 375 if (MRI.hasOneDef(Reg)) 376 return; 377 378 // Add output dependence to the next nearest def of this vreg. 379 // 380 // Unless this definition is dead, the output dependence should be 381 // transitively redundant with antidependencies from this definition's 382 // uses. We're conservative for now until we have a way to guarantee the uses 383 // are not eliminated sometime during scheduling. The output dependence edge 384 // is also useful if output latency exceeds def-use latency. 385 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg); 386 if (DefI == VRegDefs.end()) 387 VRegDefs.insert(VReg2SUnit(Reg, SU)); 388 else { 389 SUnit *DefSU = DefI->SU; 390 if (DefSU != SU && DefSU != &ExitSU) { 391 SDep Dep(SU, SDep::Output, Reg); 392 Dep.setLatency( 393 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); 394 DefSU->addPred(Dep); 395 } 396 DefI->SU = SU; 397 } 398} 399 400/// addVRegUseDeps - Add a register data dependency if the instruction that 401/// defines the virtual register used at OperIdx is mapped to an SUnit. Add a 402/// register antidependency from this SUnit to instructions that occur later in 403/// the same scheduling region if they write the virtual register. 404/// 405/// TODO: Handle ExitSU "uses" properly. 406void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) { 407 MachineInstr *MI = SU->getInstr(); 408 unsigned Reg = MI->getOperand(OperIdx).getReg(); 409 410 // Record this local VReg use. 411 VRegUses.insert(VReg2SUnit(Reg, SU)); 412 413 // Lookup this operand's reaching definition. 414 assert(LIS && "vreg dependencies requires LiveIntervals"); 415 LiveRangeQuery LRQ(LIS->getInterval(Reg), LIS->getInstructionIndex(MI)); 416 VNInfo *VNI = LRQ.valueIn(); 417 418 // VNI will be valid because MachineOperand::readsReg() is checked by caller. 419 assert(VNI && "No value to read by operand"); 420 MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def); 421 // Phis and other noninstructions (after coalescing) have a NULL Def. 422 if (Def) { 423 SUnit *DefSU = getSUnit(Def); 424 if (DefSU) { 425 // The reaching Def lives within this scheduling region. 426 // Create a data dependence. 427 SDep dep(DefSU, SDep::Data, Reg); 428 // Adjust the dependence latency using operand def/use information, then 429 // allow the target to perform its own adjustments. 430 int DefOp = Def->findRegisterDefOperandIdx(Reg); 431 dep.setLatency(SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx)); 432 433 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>(); 434 ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep)); 435 SU->addPred(dep); 436 } 437 } 438 439 // Add antidependence to the following def of the vreg it uses. 440 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg); 441 if (DefI != VRegDefs.end() && DefI->SU != SU) 442 DefI->SU->addPred(SDep(SU, SDep::Anti, Reg)); 443} 444 445/// Return true if MI is an instruction we are unable to reason about 446/// (like a call or something with unmodeled side effects). 447static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) { 448 if (MI->isCall() || MI->hasUnmodeledSideEffects() || 449 (MI->hasOrderedMemoryRef() && 450 (!MI->mayLoad() || !MI->isInvariantLoad(AA)))) 451 return true; 452 return false; 453} 454 455// This MI might have either incomplete info, or known to be unsafe 456// to deal with (i.e. volatile object). 457static inline bool isUnsafeMemoryObject(MachineInstr *MI, 458 const MachineFrameInfo *MFI) { 459 if (!MI || MI->memoperands_empty()) 460 return true; 461 // We purposefully do no check for hasOneMemOperand() here 462 // in hope to trigger an assert downstream in order to 463 // finish implementation. 464 if ((*MI->memoperands_begin())->isVolatile() || 465 MI->hasUnmodeledSideEffects()) 466 return true; 467 const Value *V = (*MI->memoperands_begin())->getValue(); 468 if (!V) 469 return true; 470 471 SmallVector<Value *, 4> Objs; 472 getUnderlyingObjects(V, Objs); 473 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), 474 IE = Objs.end(); I != IE; ++I) { 475 V = *I; 476 477 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) { 478 // Similarly to getUnderlyingObjectForInstr: 479 // For now, ignore PseudoSourceValues which may alias LLVM IR values 480 // because the code that uses this function has no way to cope with 481 // such aliases. 482 if (PSV->isAliased(MFI)) 483 return true; 484 } 485 486 // Does this pointer refer to a distinct and identifiable object? 487 if (!isIdentifiedObject(V)) 488 return true; 489 } 490 491 return false; 492} 493 494/// This returns true if the two MIs need a chain edge betwee them. 495/// If these are not even memory operations, we still may need 496/// chain deps between them. The question really is - could 497/// these two MIs be reordered during scheduling from memory dependency 498/// point of view. 499static bool MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI, 500 MachineInstr *MIa, 501 MachineInstr *MIb) { 502 // Cover a trivial case - no edge is need to itself. 503 if (MIa == MIb) 504 return false; 505 506 if (isUnsafeMemoryObject(MIa, MFI) || isUnsafeMemoryObject(MIb, MFI)) 507 return true; 508 509 // If we are dealing with two "normal" loads, we do not need an edge 510 // between them - they could be reordered. 511 if (!MIa->mayStore() && !MIb->mayStore()) 512 return false; 513 514 // To this point analysis is generic. From here on we do need AA. 515 if (!AA) 516 return true; 517 518 MachineMemOperand *MMOa = *MIa->memoperands_begin(); 519 MachineMemOperand *MMOb = *MIb->memoperands_begin(); 520 521 // FIXME: Need to handle multiple memory operands to support all targets. 522 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand()) 523 llvm_unreachable("Multiple memory operands."); 524 525 // The following interface to AA is fashioned after DAGCombiner::isAlias 526 // and operates with MachineMemOperand offset with some important 527 // assumptions: 528 // - LLVM fundamentally assumes flat address spaces. 529 // - MachineOperand offset can *only* result from legalization and 530 // cannot affect queries other than the trivial case of overlap 531 // checking. 532 // - These offsets never wrap and never step outside 533 // of allocated objects. 534 // - There should never be any negative offsets here. 535 // 536 // FIXME: Modify API to hide this math from "user" 537 // FIXME: Even before we go to AA we can reason locally about some 538 // memory objects. It can save compile time, and possibly catch some 539 // corner cases not currently covered. 540 541 assert ((MMOa->getOffset() >= 0) && "Negative MachineMemOperand offset"); 542 assert ((MMOb->getOffset() >= 0) && "Negative MachineMemOperand offset"); 543 544 int64_t MinOffset = std::min(MMOa->getOffset(), MMOb->getOffset()); 545 int64_t Overlapa = MMOa->getSize() + MMOa->getOffset() - MinOffset; 546 int64_t Overlapb = MMOb->getSize() + MMOb->getOffset() - MinOffset; 547 548 AliasAnalysis::AliasResult AAResult = AA->alias( 549 AliasAnalysis::Location(MMOa->getValue(), Overlapa, 550 MMOa->getTBAAInfo()), 551 AliasAnalysis::Location(MMOb->getValue(), Overlapb, 552 MMOb->getTBAAInfo())); 553 554 return (AAResult != AliasAnalysis::NoAlias); 555} 556 557/// This recursive function iterates over chain deps of SUb looking for 558/// "latest" node that needs a chain edge to SUa. 559static unsigned 560iterateChainSucc(AliasAnalysis *AA, const MachineFrameInfo *MFI, 561 SUnit *SUa, SUnit *SUb, SUnit *ExitSU, unsigned *Depth, 562 SmallPtrSet<const SUnit*, 16> &Visited) { 563 if (!SUa || !SUb || SUb == ExitSU) 564 return *Depth; 565 566 // Remember visited nodes. 567 if (!Visited.insert(SUb)) 568 return *Depth; 569 // If there is _some_ dependency already in place, do not 570 // descend any further. 571 // TODO: Need to make sure that if that dependency got eliminated or ignored 572 // for any reason in the future, we would not violate DAG topology. 573 // Currently it does not happen, but makes an implicit assumption about 574 // future implementation. 575 // 576 // Independently, if we encounter node that is some sort of global 577 // object (like a call) we already have full set of dependencies to it 578 // and we can stop descending. 579 if (SUa->isSucc(SUb) || 580 isGlobalMemoryObject(AA, SUb->getInstr())) 581 return *Depth; 582 583 // If we do need an edge, or we have exceeded depth budget, 584 // add that edge to the predecessors chain of SUb, 585 // and stop descending. 586 if (*Depth > 200 || 587 MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) { 588 SUb->addPred(SDep(SUa, SDep::MayAliasMem)); 589 return *Depth; 590 } 591 // Track current depth. 592 (*Depth)++; 593 // Iterate over chain dependencies only. 594 for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E = SUb->Succs.end(); 595 I != E; ++I) 596 if (I->isCtrl()) 597 iterateChainSucc (AA, MFI, SUa, I->getSUnit(), ExitSU, Depth, Visited); 598 return *Depth; 599} 600 601/// This function assumes that "downward" from SU there exist 602/// tail/leaf of already constructed DAG. It iterates downward and 603/// checks whether SU can be aliasing any node dominated 604/// by it. 605static void adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI, 606 SUnit *SU, SUnit *ExitSU, std::set<SUnit *> &CheckList, 607 unsigned LatencyToLoad) { 608 if (!SU) 609 return; 610 611 SmallPtrSet<const SUnit*, 16> Visited; 612 unsigned Depth = 0; 613 614 for (std::set<SUnit *>::iterator I = CheckList.begin(), IE = CheckList.end(); 615 I != IE; ++I) { 616 if (SU == *I) 617 continue; 618 if (MIsNeedChainEdge(AA, MFI, SU->getInstr(), (*I)->getInstr())) { 619 SDep Dep(SU, SDep::MayAliasMem); 620 Dep.setLatency(((*I)->getInstr()->mayLoad()) ? LatencyToLoad : 0); 621 (*I)->addPred(Dep); 622 } 623 // Now go through all the chain successors and iterate from them. 624 // Keep track of visited nodes. 625 for (SUnit::const_succ_iterator J = (*I)->Succs.begin(), 626 JE = (*I)->Succs.end(); J != JE; ++J) 627 if (J->isCtrl()) 628 iterateChainSucc (AA, MFI, SU, J->getSUnit(), 629 ExitSU, &Depth, Visited); 630 } 631} 632 633/// Check whether two objects need a chain edge, if so, add it 634/// otherwise remember the rejected SU. 635static inline 636void addChainDependency (AliasAnalysis *AA, const MachineFrameInfo *MFI, 637 SUnit *SUa, SUnit *SUb, 638 std::set<SUnit *> &RejectList, 639 unsigned TrueMemOrderLatency = 0, 640 bool isNormalMemory = false) { 641 // If this is a false dependency, 642 // do not add the edge, but rememeber the rejected node. 643 if (!AA || MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) { 644 SDep Dep(SUa, isNormalMemory ? SDep::MayAliasMem : SDep::Barrier); 645 Dep.setLatency(TrueMemOrderLatency); 646 SUb->addPred(Dep); 647 } 648 else { 649 // Duplicate entries should be ignored. 650 RejectList.insert(SUb); 651 DEBUG(dbgs() << "\tReject chain dep between SU(" 652 << SUa->NodeNum << ") and SU(" 653 << SUb->NodeNum << ")\n"); 654 } 655} 656 657/// Create an SUnit for each real instruction, numbered in top-down toplological 658/// order. The instruction order A < B, implies that no edge exists from B to A. 659/// 660/// Map each real instruction to its SUnit. 661/// 662/// After initSUnits, the SUnits vector cannot be resized and the scheduler may 663/// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs 664/// instead of pointers. 665/// 666/// MachineScheduler relies on initSUnits numbering the nodes by their order in 667/// the original instruction list. 668void ScheduleDAGInstrs::initSUnits() { 669 // We'll be allocating one SUnit for each real instruction in the region, 670 // which is contained within a basic block. 671 SUnits.reserve(NumRegionInstrs); 672 673 for (MachineBasicBlock::iterator I = RegionBegin; I != RegionEnd; ++I) { 674 MachineInstr *MI = I; 675 if (MI->isDebugValue()) 676 continue; 677 678 SUnit *SU = newSUnit(MI); 679 MISUnitMap[MI] = SU; 680 681 SU->isCall = MI->isCall(); 682 SU->isCommutable = MI->isCommutable(); 683 684 // Assign the Latency field of SU using target-provided information. 685 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr()); 686 } 687} 688 689/// If RegPressure is non null, compute register pressure as a side effect. The 690/// DAG builder is an efficient place to do it because it already visits 691/// operands. 692void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA, 693 RegPressureTracker *RPTracker) { 694 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>(); 695 bool UseAA = EnableAASchedMI.getNumOccurrences() > 0 ? EnableAASchedMI 696 : ST.useAA(); 697 AliasAnalysis *AAForDep = UseAA ? AA : 0; 698 699 // Create an SUnit for each real instruction. 700 initSUnits(); 701 702 // We build scheduling units by walking a block's instruction list from bottom 703 // to top. 704 705 // Remember where a generic side-effecting instruction is as we procede. 706 SUnit *BarrierChain = 0, *AliasChain = 0; 707 708 // Memory references to specific known memory locations are tracked 709 // so that they can be given more precise dependencies. We track 710 // separately the known memory locations that may alias and those 711 // that are known not to alias 712 MapVector<const Value *, SUnit *> AliasMemDefs, NonAliasMemDefs; 713 MapVector<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses; 714 std::set<SUnit*> RejectMemNodes; 715 716 // Remove any stale debug info; sometimes BuildSchedGraph is called again 717 // without emitting the info from the previous call. 718 DbgValues.clear(); 719 FirstDbgValue = NULL; 720 721 assert(Defs.empty() && Uses.empty() && 722 "Only BuildGraph should update Defs/Uses"); 723 Defs.setUniverse(TRI->getNumRegs()); 724 Uses.setUniverse(TRI->getNumRegs()); 725 726 assert(VRegDefs.empty() && "Only BuildSchedGraph may access VRegDefs"); 727 VRegUses.clear(); 728 VRegDefs.setUniverse(MRI.getNumVirtRegs()); 729 VRegUses.setUniverse(MRI.getNumVirtRegs()); 730 731 // Model data dependencies between instructions being scheduled and the 732 // ExitSU. 733 addSchedBarrierDeps(); 734 735 // Walk the list of instructions, from bottom moving up. 736 MachineInstr *DbgMI = NULL; 737 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin; 738 MII != MIE; --MII) { 739 MachineInstr *MI = prior(MII); 740 if (MI && DbgMI) { 741 DbgValues.push_back(std::make_pair(DbgMI, MI)); 742 DbgMI = NULL; 743 } 744 745 if (MI->isDebugValue()) { 746 DbgMI = MI; 747 continue; 748 } 749 if (RPTracker) { 750 RPTracker->recede(); 751 assert(RPTracker->getPos() == prior(MII) && "RPTracker can't find MI"); 752 } 753 754 assert((CanHandleTerminators || (!MI->isTerminator() && !MI->isLabel())) && 755 "Cannot schedule terminators or labels!"); 756 757 SUnit *SU = MISUnitMap[MI]; 758 assert(SU && "No SUnit mapped to this MI"); 759 760 // Add register-based dependencies (data, anti, and output). 761 bool HasVRegDef = false; 762 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) { 763 const MachineOperand &MO = MI->getOperand(j); 764 if (!MO.isReg()) continue; 765 unsigned Reg = MO.getReg(); 766 if (Reg == 0) continue; 767 768 if (TRI->isPhysicalRegister(Reg)) 769 addPhysRegDeps(SU, j); 770 else { 771 assert(!IsPostRA && "Virtual register encountered!"); 772 if (MO.isDef()) { 773 HasVRegDef = true; 774 addVRegDefDeps(SU, j); 775 } 776 else if (MO.readsReg()) // ignore undef operands 777 addVRegUseDeps(SU, j); 778 } 779 } 780 // If we haven't seen any uses in this scheduling region, create a 781 // dependence edge to ExitSU to model the live-out latency. This is required 782 // for vreg defs with no in-region use, and prefetches with no vreg def. 783 // 784 // FIXME: NumDataSuccs would be more precise than NumSuccs here. This 785 // check currently relies on being called before adding chain deps. 786 if (SU->NumSuccs == 0 && SU->Latency > 1 787 && (HasVRegDef || MI->mayLoad())) { 788 SDep Dep(SU, SDep::Artificial); 789 Dep.setLatency(SU->Latency - 1); 790 ExitSU.addPred(Dep); 791 } 792 793 // Add chain dependencies. 794 // Chain dependencies used to enforce memory order should have 795 // latency of 0 (except for true dependency of Store followed by 796 // aliased Load... we estimate that with a single cycle of latency 797 // assuming the hardware will bypass) 798 // Note that isStoreToStackSlot and isLoadFromStackSLot are not usable 799 // after stack slots are lowered to actual addresses. 800 // TODO: Use an AliasAnalysis and do real alias-analysis queries, and 801 // produce more precise dependence information. 802 unsigned TrueMemOrderLatency = MI->mayStore() ? 1 : 0; 803 if (isGlobalMemoryObject(AA, MI)) { 804 // Be conservative with these and add dependencies on all memory 805 // references, even those that are known to not alias. 806 for (MapVector<const Value *, SUnit *>::iterator I = 807 NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) { 808 I->second->addPred(SDep(SU, SDep::Barrier)); 809 } 810 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I = 811 NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) { 812 for (unsigned i = 0, e = I->second.size(); i != e; ++i) { 813 SDep Dep(SU, SDep::Barrier); 814 Dep.setLatency(TrueMemOrderLatency); 815 I->second[i]->addPred(Dep); 816 } 817 } 818 // Add SU to the barrier chain. 819 if (BarrierChain) 820 BarrierChain->addPred(SDep(SU, SDep::Barrier)); 821 BarrierChain = SU; 822 // This is a barrier event that acts as a pivotal node in the DAG, 823 // so it is safe to clear list of exposed nodes. 824 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, 825 TrueMemOrderLatency); 826 RejectMemNodes.clear(); 827 NonAliasMemDefs.clear(); 828 NonAliasMemUses.clear(); 829 830 // fall-through 831 new_alias_chain: 832 // Chain all possibly aliasing memory references though SU. 833 if (AliasChain) { 834 unsigned ChainLatency = 0; 835 if (AliasChain->getInstr()->mayLoad()) 836 ChainLatency = TrueMemOrderLatency; 837 addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes, 838 ChainLatency); 839 } 840 AliasChain = SU; 841 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k) 842 addChainDependency(AAForDep, MFI, SU, PendingLoads[k], RejectMemNodes, 843 TrueMemOrderLatency); 844 for (MapVector<const Value *, SUnit *>::iterator I = AliasMemDefs.begin(), 845 E = AliasMemDefs.end(); I != E; ++I) 846 addChainDependency(AAForDep, MFI, SU, I->second, RejectMemNodes); 847 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I = 848 AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) { 849 for (unsigned i = 0, e = I->second.size(); i != e; ++i) 850 addChainDependency(AAForDep, MFI, SU, I->second[i], RejectMemNodes, 851 TrueMemOrderLatency); 852 } 853 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, 854 TrueMemOrderLatency); 855 PendingLoads.clear(); 856 AliasMemDefs.clear(); 857 AliasMemUses.clear(); 858 } else if (MI->mayStore()) { 859 UnderlyingObjectsVector Objs; 860 getUnderlyingObjectsForInstr(MI, MFI, Objs); 861 862 if (Objs.empty()) { 863 // Treat all other stores conservatively. 864 goto new_alias_chain; 865 } 866 867 bool MayAlias = false; 868 for (UnderlyingObjectsVector::iterator K = Objs.begin(), KE = Objs.end(); 869 K != KE; ++K) { 870 const Value *V = K->getPointer(); 871 bool ThisMayAlias = K->getInt(); 872 if (ThisMayAlias) 873 MayAlias = true; 874 875 // A store to a specific PseudoSourceValue. Add precise dependencies. 876 // Record the def in MemDefs, first adding a dep if there is 877 // an existing def. 878 MapVector<const Value *, SUnit *>::iterator I = 879 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V)); 880 MapVector<const Value *, SUnit *>::iterator IE = 881 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end()); 882 if (I != IE) { 883 addChainDependency(AAForDep, MFI, SU, I->second, RejectMemNodes, 884 0, true); 885 I->second = SU; 886 } else { 887 if (ThisMayAlias) 888 AliasMemDefs[V] = SU; 889 else 890 NonAliasMemDefs[V] = SU; 891 } 892 // Handle the uses in MemUses, if there are any. 893 MapVector<const Value *, std::vector<SUnit *> >::iterator J = 894 ((ThisMayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V)); 895 MapVector<const Value *, std::vector<SUnit *> >::iterator JE = 896 ((ThisMayAlias) ? AliasMemUses.end() : NonAliasMemUses.end()); 897 if (J != JE) { 898 for (unsigned i = 0, e = J->second.size(); i != e; ++i) 899 addChainDependency(AAForDep, MFI, SU, J->second[i], RejectMemNodes, 900 TrueMemOrderLatency, true); 901 J->second.clear(); 902 } 903 } 904 if (MayAlias) { 905 // Add dependencies from all the PendingLoads, i.e. loads 906 // with no underlying object. 907 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k) 908 addChainDependency(AAForDep, MFI, SU, PendingLoads[k], RejectMemNodes, 909 TrueMemOrderLatency); 910 // Add dependence on alias chain, if needed. 911 if (AliasChain) 912 addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes); 913 // But we also should check dependent instructions for the 914 // SU in question. 915 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, 916 TrueMemOrderLatency); 917 } 918 // Add dependence on barrier chain, if needed. 919 // There is no point to check aliasing on barrier event. Even if 920 // SU and barrier _could_ be reordered, they should not. In addition, 921 // we have lost all RejectMemNodes below barrier. 922 if (BarrierChain) 923 BarrierChain->addPred(SDep(SU, SDep::Barrier)); 924 925 if (!ExitSU.isPred(SU)) 926 // Push store's up a bit to avoid them getting in between cmp 927 // and branches. 928 ExitSU.addPred(SDep(SU, SDep::Artificial)); 929 } else if (MI->mayLoad()) { 930 bool MayAlias = true; 931 if (MI->isInvariantLoad(AA)) { 932 // Invariant load, no chain dependencies needed! 933 } else { 934 UnderlyingObjectsVector Objs; 935 getUnderlyingObjectsForInstr(MI, MFI, Objs); 936 937 if (Objs.empty()) { 938 // A load with no underlying object. Depend on all 939 // potentially aliasing stores. 940 for (MapVector<const Value *, SUnit *>::iterator I = 941 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I) 942 addChainDependency(AAForDep, MFI, SU, I->second, RejectMemNodes); 943 944 PendingLoads.push_back(SU); 945 MayAlias = true; 946 } else { 947 MayAlias = false; 948 } 949 950 for (UnderlyingObjectsVector::iterator 951 J = Objs.begin(), JE = Objs.end(); J != JE; ++J) { 952 const Value *V = J->getPointer(); 953 bool ThisMayAlias = J->getInt(); 954 955 if (ThisMayAlias) 956 MayAlias = true; 957 958 // A load from a specific PseudoSourceValue. Add precise dependencies. 959 MapVector<const Value *, SUnit *>::iterator I = 960 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V)); 961 MapVector<const Value *, SUnit *>::iterator IE = 962 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end()); 963 if (I != IE) 964 addChainDependency(AAForDep, MFI, SU, I->second, RejectMemNodes, 965 0, true); 966 if (ThisMayAlias) 967 AliasMemUses[V].push_back(SU); 968 else 969 NonAliasMemUses[V].push_back(SU); 970 } 971 if (MayAlias) 972 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, /*Latency=*/0); 973 // Add dependencies on alias and barrier chains, if needed. 974 if (MayAlias && AliasChain) 975 addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes); 976 if (BarrierChain) 977 BarrierChain->addPred(SDep(SU, SDep::Barrier)); 978 } 979 } 980 } 981 if (DbgMI) 982 FirstDbgValue = DbgMI; 983 984 Defs.clear(); 985 Uses.clear(); 986 VRegDefs.clear(); 987 PendingLoads.clear(); 988} 989 990/// Compute the max cyclic critical path through the DAG. For loops that span 991/// basic blocks, MachineTraceMetrics should be used for this instead. 992unsigned ScheduleDAGInstrs::computeCyclicCriticalPath() { 993 // This only applies to single block loop. 994 if (!BB->isSuccessor(BB)) 995 return 0; 996 997 unsigned MaxCyclicLatency = 0; 998 // Visit each live out vreg def to find def/use pairs that cross iterations. 999 for (SUnit::const_pred_iterator 1000 PI = ExitSU.Preds.begin(), PE = ExitSU.Preds.end(); PI != PE; ++PI) { 1001 MachineInstr *MI = PI->getSUnit()->getInstr(); 1002 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1003 const MachineOperand &MO = MI->getOperand(i); 1004 if (!MO.isReg() || !MO.isDef()) 1005 break; 1006 unsigned Reg = MO.getReg(); 1007 if (!Reg || TRI->isPhysicalRegister(Reg)) 1008 continue; 1009 1010 const LiveInterval &LI = LIS->getInterval(Reg); 1011 unsigned LiveOutHeight = PI->getSUnit()->getHeight(); 1012 unsigned LiveOutDepth = PI->getSUnit()->getDepth() + PI->getLatency(); 1013 // Visit all local users of the vreg def. 1014 for (VReg2UseMap::iterator 1015 UI = VRegUses.find(Reg); UI != VRegUses.end(); ++UI) { 1016 if (UI->SU == &ExitSU) 1017 continue; 1018 1019 // Only consider uses of the phi. 1020 LiveRangeQuery LRQ(LI, LIS->getInstructionIndex(UI->SU->getInstr())); 1021 if (!LRQ.valueIn()->isPHIDef()) 1022 continue; 1023 1024 // Cheat a bit and assume that a path spanning two iterations is a 1025 // cycle, which could overestimate in strange cases. This allows cyclic 1026 // latency to be estimated as the minimum height or depth slack. 1027 unsigned CyclicLatency = 0; 1028 if (LiveOutDepth > UI->SU->getDepth()) 1029 CyclicLatency = LiveOutDepth - UI->SU->getDepth(); 1030 unsigned LiveInHeight = UI->SU->getHeight() + PI->getLatency(); 1031 if (LiveInHeight > LiveOutHeight) { 1032 if (LiveInHeight - LiveOutHeight < CyclicLatency) 1033 CyclicLatency = LiveInHeight - LiveOutHeight; 1034 } 1035 else 1036 CyclicLatency = 0; 1037 DEBUG(dbgs() << "Cyclic Path: SU(" << PI->getSUnit()->NodeNum 1038 << ") -> SU(" << UI->SU->NodeNum << ") = " 1039 << CyclicLatency << "\n"); 1040 if (CyclicLatency > MaxCyclicLatency) 1041 MaxCyclicLatency = CyclicLatency; 1042 } 1043 } 1044 } 1045 DEBUG(dbgs() << "Cyclic Critical Path: " << MaxCyclicLatency << "\n"); 1046 return MaxCyclicLatency; 1047} 1048 1049void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const { 1050#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 1051 SU->getInstr()->dump(); 1052#endif 1053} 1054 1055std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const { 1056 std::string s; 1057 raw_string_ostream oss(s); 1058 if (SU == &EntrySU) 1059 oss << "<entry>"; 1060 else if (SU == &ExitSU) 1061 oss << "<exit>"; 1062 else 1063 SU->getInstr()->print(oss, &TM, /*SkipOpers=*/true); 1064 return oss.str(); 1065} 1066 1067/// Return the basic block label. It is not necessarilly unique because a block 1068/// contains multiple scheduling regions. But it is fine for visualization. 1069std::string ScheduleDAGInstrs::getDAGName() const { 1070 return "dag." + BB->getFullName(); 1071} 1072 1073//===----------------------------------------------------------------------===// 1074// SchedDFSResult Implementation 1075//===----------------------------------------------------------------------===// 1076 1077namespace llvm { 1078/// \brief Internal state used to compute SchedDFSResult. 1079class SchedDFSImpl { 1080 SchedDFSResult &R; 1081 1082 /// Join DAG nodes into equivalence classes by their subtree. 1083 IntEqClasses SubtreeClasses; 1084 /// List PredSU, SuccSU pairs that represent data edges between subtrees. 1085 std::vector<std::pair<const SUnit*, const SUnit*> > ConnectionPairs; 1086 1087 struct RootData { 1088 unsigned NodeID; 1089 unsigned ParentNodeID; // Parent node (member of the parent subtree). 1090 unsigned SubInstrCount; // Instr count in this tree only, not children. 1091 1092 RootData(unsigned id): NodeID(id), 1093 ParentNodeID(SchedDFSResult::InvalidSubtreeID), 1094 SubInstrCount(0) {} 1095 1096 unsigned getSparseSetIndex() const { return NodeID; } 1097 }; 1098 1099 SparseSet<RootData> RootSet; 1100 1101public: 1102 SchedDFSImpl(SchedDFSResult &r): R(r), SubtreeClasses(R.DFSNodeData.size()) { 1103 RootSet.setUniverse(R.DFSNodeData.size()); 1104 } 1105 1106 /// Return true if this node been visited by the DFS traversal. 1107 /// 1108 /// During visitPostorderNode the Node's SubtreeID is assigned to the Node 1109 /// ID. Later, SubtreeID is updated but remains valid. 1110 bool isVisited(const SUnit *SU) const { 1111 return R.DFSNodeData[SU->NodeNum].SubtreeID 1112 != SchedDFSResult::InvalidSubtreeID; 1113 } 1114 1115 /// Initialize this node's instruction count. We don't need to flag the node 1116 /// visited until visitPostorder because the DAG cannot have cycles. 1117 void visitPreorder(const SUnit *SU) { 1118 R.DFSNodeData[SU->NodeNum].InstrCount = 1119 SU->getInstr()->isTransient() ? 0 : 1; 1120 } 1121 1122 /// Called once for each node after all predecessors are visited. Revisit this 1123 /// node's predecessors and potentially join them now that we know the ILP of 1124 /// the other predecessors. 1125 void visitPostorderNode(const SUnit *SU) { 1126 // Mark this node as the root of a subtree. It may be joined with its 1127 // successors later. 1128 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum; 1129 RootData RData(SU->NodeNum); 1130 RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1; 1131 1132 // If any predecessors are still in their own subtree, they either cannot be 1133 // joined or are large enough to remain separate. If this parent node's 1134 // total instruction count is not greater than a child subtree by at least 1135 // the subtree limit, then try to join it now since splitting subtrees is 1136 // only useful if multiple high-pressure paths are possible. 1137 unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount; 1138 for (SUnit::const_pred_iterator 1139 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) { 1140 if (PI->getKind() != SDep::Data) 1141 continue; 1142 unsigned PredNum = PI->getSUnit()->NodeNum; 1143 if ((InstrCount - R.DFSNodeData[PredNum].InstrCount) < R.SubtreeLimit) 1144 joinPredSubtree(*PI, SU, /*CheckLimit=*/false); 1145 1146 // Either link or merge the TreeData entry from the child to the parent. 1147 if (R.DFSNodeData[PredNum].SubtreeID == PredNum) { 1148 // If the predecessor's parent is invalid, this is a tree edge and the 1149 // current node is the parent. 1150 if (RootSet[PredNum].ParentNodeID == SchedDFSResult::InvalidSubtreeID) 1151 RootSet[PredNum].ParentNodeID = SU->NodeNum; 1152 } 1153 else if (RootSet.count(PredNum)) { 1154 // The predecessor is not a root, but is still in the root set. This 1155 // must be the new parent that it was just joined to. Note that 1156 // RootSet[PredNum].ParentNodeID may either be invalid or may still be 1157 // set to the original parent. 1158 RData.SubInstrCount += RootSet[PredNum].SubInstrCount; 1159 RootSet.erase(PredNum); 1160 } 1161 } 1162 RootSet[SU->NodeNum] = RData; 1163 } 1164 1165 /// Called once for each tree edge after calling visitPostOrderNode on the 1166 /// predecessor. Increment the parent node's instruction count and 1167 /// preemptively join this subtree to its parent's if it is small enough. 1168 void visitPostorderEdge(const SDep &PredDep, const SUnit *Succ) { 1169 R.DFSNodeData[Succ->NodeNum].InstrCount 1170 += R.DFSNodeData[PredDep.getSUnit()->NodeNum].InstrCount; 1171 joinPredSubtree(PredDep, Succ); 1172 } 1173 1174 /// Add a connection for cross edges. 1175 void visitCrossEdge(const SDep &PredDep, const SUnit *Succ) { 1176 ConnectionPairs.push_back(std::make_pair(PredDep.getSUnit(), Succ)); 1177 } 1178 1179 /// Set each node's subtree ID to the representative ID and record connections 1180 /// between trees. 1181 void finalize() { 1182 SubtreeClasses.compress(); 1183 R.DFSTreeData.resize(SubtreeClasses.getNumClasses()); 1184 assert(SubtreeClasses.getNumClasses() == RootSet.size() 1185 && "number of roots should match trees"); 1186 for (SparseSet<RootData>::const_iterator 1187 RI = RootSet.begin(), RE = RootSet.end(); RI != RE; ++RI) { 1188 unsigned TreeID = SubtreeClasses[RI->NodeID]; 1189 if (RI->ParentNodeID != SchedDFSResult::InvalidSubtreeID) 1190 R.DFSTreeData[TreeID].ParentTreeID = SubtreeClasses[RI->ParentNodeID]; 1191 R.DFSTreeData[TreeID].SubInstrCount = RI->SubInstrCount; 1192 // Note that SubInstrCount may be greater than InstrCount if we joined 1193 // subtrees across a cross edge. InstrCount will be attributed to the 1194 // original parent, while SubInstrCount will be attributed to the joined 1195 // parent. 1196 } 1197 R.SubtreeConnections.resize(SubtreeClasses.getNumClasses()); 1198 R.SubtreeConnectLevels.resize(SubtreeClasses.getNumClasses()); 1199 DEBUG(dbgs() << R.getNumSubtrees() << " subtrees:\n"); 1200 for (unsigned Idx = 0, End = R.DFSNodeData.size(); Idx != End; ++Idx) { 1201 R.DFSNodeData[Idx].SubtreeID = SubtreeClasses[Idx]; 1202 DEBUG(dbgs() << " SU(" << Idx << ") in tree " 1203 << R.DFSNodeData[Idx].SubtreeID << '\n'); 1204 } 1205 for (std::vector<std::pair<const SUnit*, const SUnit*> >::const_iterator 1206 I = ConnectionPairs.begin(), E = ConnectionPairs.end(); 1207 I != E; ++I) { 1208 unsigned PredTree = SubtreeClasses[I->first->NodeNum]; 1209 unsigned SuccTree = SubtreeClasses[I->second->NodeNum]; 1210 if (PredTree == SuccTree) 1211 continue; 1212 unsigned Depth = I->first->getDepth(); 1213 addConnection(PredTree, SuccTree, Depth); 1214 addConnection(SuccTree, PredTree, Depth); 1215 } 1216 } 1217 1218protected: 1219 /// Join the predecessor subtree with the successor that is its DFS 1220 /// parent. Apply some heuristics before joining. 1221 bool joinPredSubtree(const SDep &PredDep, const SUnit *Succ, 1222 bool CheckLimit = true) { 1223 assert(PredDep.getKind() == SDep::Data && "Subtrees are for data edges"); 1224 1225 // Check if the predecessor is already joined. 1226 const SUnit *PredSU = PredDep.getSUnit(); 1227 unsigned PredNum = PredSU->NodeNum; 1228 if (R.DFSNodeData[PredNum].SubtreeID != PredNum) 1229 return false; 1230 1231 // Four is the magic number of successors before a node is considered a 1232 // pinch point. 1233 unsigned NumDataSucs = 0; 1234 for (SUnit::const_succ_iterator SI = PredSU->Succs.begin(), 1235 SE = PredSU->Succs.end(); SI != SE; ++SI) { 1236 if (SI->getKind() == SDep::Data) { 1237 if (++NumDataSucs >= 4) 1238 return false; 1239 } 1240 } 1241 if (CheckLimit && R.DFSNodeData[PredNum].InstrCount > R.SubtreeLimit) 1242 return false; 1243 R.DFSNodeData[PredNum].SubtreeID = Succ->NodeNum; 1244 SubtreeClasses.join(Succ->NodeNum, PredNum); 1245 return true; 1246 } 1247 1248 /// Called by finalize() to record a connection between trees. 1249 void addConnection(unsigned FromTree, unsigned ToTree, unsigned Depth) { 1250 if (!Depth) 1251 return; 1252 1253 do { 1254 SmallVectorImpl<SchedDFSResult::Connection> &Connections = 1255 R.SubtreeConnections[FromTree]; 1256 for (SmallVectorImpl<SchedDFSResult::Connection>::iterator 1257 I = Connections.begin(), E = Connections.end(); I != E; ++I) { 1258 if (I->TreeID == ToTree) { 1259 I->Level = std::max(I->Level, Depth); 1260 return; 1261 } 1262 } 1263 Connections.push_back(SchedDFSResult::Connection(ToTree, Depth)); 1264 FromTree = R.DFSTreeData[FromTree].ParentTreeID; 1265 } while (FromTree != SchedDFSResult::InvalidSubtreeID); 1266 } 1267}; 1268} // namespace llvm 1269 1270namespace { 1271/// \brief Manage the stack used by a reverse depth-first search over the DAG. 1272class SchedDAGReverseDFS { 1273 std::vector<std::pair<const SUnit*, SUnit::const_pred_iterator> > DFSStack; 1274public: 1275 bool isComplete() const { return DFSStack.empty(); } 1276 1277 void follow(const SUnit *SU) { 1278 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin())); 1279 } 1280 void advance() { ++DFSStack.back().second; } 1281 1282 const SDep *backtrack() { 1283 DFSStack.pop_back(); 1284 return DFSStack.empty() ? 0 : llvm::prior(DFSStack.back().second); 1285 } 1286 1287 const SUnit *getCurr() const { return DFSStack.back().first; } 1288 1289 SUnit::const_pred_iterator getPred() const { return DFSStack.back().second; } 1290 1291 SUnit::const_pred_iterator getPredEnd() const { 1292 return getCurr()->Preds.end(); 1293 } 1294}; 1295} // anonymous 1296 1297static bool hasDataSucc(const SUnit *SU) { 1298 for (SUnit::const_succ_iterator 1299 SI = SU->Succs.begin(), SE = SU->Succs.end(); SI != SE; ++SI) { 1300 if (SI->getKind() == SDep::Data && !SI->getSUnit()->isBoundaryNode()) 1301 return true; 1302 } 1303 return false; 1304} 1305 1306/// Compute an ILP metric for all nodes in the subDAG reachable via depth-first 1307/// search from this root. 1308void SchedDFSResult::compute(ArrayRef<SUnit> SUnits) { 1309 if (!IsBottomUp) 1310 llvm_unreachable("Top-down ILP metric is unimplemnted"); 1311 1312 SchedDFSImpl Impl(*this); 1313 for (ArrayRef<SUnit>::const_iterator 1314 SI = SUnits.begin(), SE = SUnits.end(); SI != SE; ++SI) { 1315 const SUnit *SU = &*SI; 1316 if (Impl.isVisited(SU) || hasDataSucc(SU)) 1317 continue; 1318 1319 SchedDAGReverseDFS DFS; 1320 Impl.visitPreorder(SU); 1321 DFS.follow(SU); 1322 for (;;) { 1323 // Traverse the leftmost path as far as possible. 1324 while (DFS.getPred() != DFS.getPredEnd()) { 1325 const SDep &PredDep = *DFS.getPred(); 1326 DFS.advance(); 1327 // Ignore non-data edges. 1328 if (PredDep.getKind() != SDep::Data 1329 || PredDep.getSUnit()->isBoundaryNode()) { 1330 continue; 1331 } 1332 // An already visited edge is a cross edge, assuming an acyclic DAG. 1333 if (Impl.isVisited(PredDep.getSUnit())) { 1334 Impl.visitCrossEdge(PredDep, DFS.getCurr()); 1335 continue; 1336 } 1337 Impl.visitPreorder(PredDep.getSUnit()); 1338 DFS.follow(PredDep.getSUnit()); 1339 } 1340 // Visit the top of the stack in postorder and backtrack. 1341 const SUnit *Child = DFS.getCurr(); 1342 const SDep *PredDep = DFS.backtrack(); 1343 Impl.visitPostorderNode(Child); 1344 if (PredDep) 1345 Impl.visitPostorderEdge(*PredDep, DFS.getCurr()); 1346 if (DFS.isComplete()) 1347 break; 1348 } 1349 } 1350 Impl.finalize(); 1351} 1352 1353/// The root of the given SubtreeID was just scheduled. For all subtrees 1354/// connected to this tree, record the depth of the connection so that the 1355/// nearest connected subtrees can be prioritized. 1356void SchedDFSResult::scheduleTree(unsigned SubtreeID) { 1357 for (SmallVectorImpl<Connection>::const_iterator 1358 I = SubtreeConnections[SubtreeID].begin(), 1359 E = SubtreeConnections[SubtreeID].end(); I != E; ++I) { 1360 SubtreeConnectLevels[I->TreeID] = 1361 std::max(SubtreeConnectLevels[I->TreeID], I->Level); 1362 DEBUG(dbgs() << " Tree: " << I->TreeID 1363 << " @" << SubtreeConnectLevels[I->TreeID] << '\n'); 1364 } 1365} 1366 1367#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 1368void ILPValue::print(raw_ostream &OS) const { 1369 OS << InstrCount << " / " << Length << " = "; 1370 if (!Length) 1371 OS << "BADILP"; 1372 else 1373 OS << format("%g", ((double)InstrCount / Length)); 1374} 1375 1376void ILPValue::dump() const { 1377 dbgs() << *this << '\n'; 1378} 1379 1380namespace llvm { 1381 1382raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val) { 1383 Val.print(OS); 1384 return OS; 1385} 1386 1387} // namespace llvm 1388#endif // !NDEBUG || LLVM_ENABLE_DUMP 1389