ScheduleDAGInstrs.cpp revision f21831073ca474601620d1a29258176b0deaedb2
1//===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the ScheduleDAGInstrs class, which implements re-scheduling 11// of MachineInstrs. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "misched" 16#include "llvm/CodeGen/ScheduleDAGInstrs.h" 17#include "llvm/ADT/MapVector.h" 18#include "llvm/ADT/SmallPtrSet.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ValueTracking.h" 22#include "llvm/CodeGen/LiveIntervalAnalysis.h" 23#include "llvm/CodeGen/MachineFunctionPass.h" 24#include "llvm/CodeGen/MachineMemOperand.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/CodeGen/RegisterPressure.h" 28#include "llvm/CodeGen/ScheduleDFS.h" 29#include "llvm/MC/MCInstrItineraries.h" 30#include "llvm/Operator.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/Support/Format.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/TargetInstrInfo.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetRegisterInfo.h" 38#include "llvm/Target/TargetSubtargetInfo.h" 39using namespace llvm; 40 41static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden, 42 cl::ZeroOrMore, cl::init(false), 43 cl::desc("Enable use of AA during MI GAD construction")); 44 45ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf, 46 const MachineLoopInfo &mli, 47 const MachineDominatorTree &mdt, 48 bool IsPostRAFlag, 49 LiveIntervals *lis) 50 : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), LIS(lis), 51 IsPostRA(IsPostRAFlag), CanHandleTerminators(false), FirstDbgValue(0) { 52 assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals"); 53 DbgValues.clear(); 54 assert(!(IsPostRA && MRI.getNumVirtRegs()) && 55 "Virtual registers must be removed prior to PostRA scheduling"); 56 57 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>(); 58 SchedModel.init(*ST.getSchedModel(), &ST, TII); 59} 60 61/// getUnderlyingObjectFromInt - This is the function that does the work of 62/// looking through basic ptrtoint+arithmetic+inttoptr sequences. 63static const Value *getUnderlyingObjectFromInt(const Value *V) { 64 do { 65 if (const Operator *U = dyn_cast<Operator>(V)) { 66 // If we find a ptrtoint, we can transfer control back to the 67 // regular getUnderlyingObjectFromInt. 68 if (U->getOpcode() == Instruction::PtrToInt) 69 return U->getOperand(0); 70 // If we find an add of a constant, a multiplied value, or a phi, it's 71 // likely that the other operand will lead us to the base 72 // object. We don't have to worry about the case where the 73 // object address is somehow being computed by the multiply, 74 // because our callers only care when the result is an 75 // identifiable object. 76 if (U->getOpcode() != Instruction::Add || 77 (!isa<ConstantInt>(U->getOperand(1)) && 78 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul && 79 !isa<PHINode>(U->getOperand(1)))) 80 return V; 81 V = U->getOperand(0); 82 } else { 83 return V; 84 } 85 assert(V->getType()->isIntegerTy() && "Unexpected operand type!"); 86 } while (1); 87} 88 89/// getUnderlyingObjects - This is a wrapper around GetUnderlyingObjects 90/// and adds support for basic ptrtoint+arithmetic+inttoptr sequences. 91static void getUnderlyingObjects(const Value *V, 92 SmallVectorImpl<Value *> &Objects) { 93 SmallPtrSet<const Value*, 16> Visited; 94 SmallVector<const Value *, 4> Working(1, V); 95 do { 96 V = Working.pop_back_val(); 97 98 SmallVector<Value *, 4> Objs; 99 GetUnderlyingObjects(const_cast<Value *>(V), Objs); 100 101 for (SmallVector<Value *, 4>::iterator I = Objs.begin(), IE = Objs.end(); 102 I != IE; ++I) { 103 V = *I; 104 if (!Visited.insert(V)) 105 continue; 106 if (Operator::getOpcode(V) == Instruction::IntToPtr) { 107 const Value *O = 108 getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0)); 109 if (O->getType()->isPointerTy()) { 110 Working.push_back(O); 111 continue; 112 } 113 } 114 Objects.push_back(const_cast<Value *>(V)); 115 } 116 } while (!Working.empty()); 117} 118 119/// getUnderlyingObjectsForInstr - If this machine instr has memory reference 120/// information and it can be tracked to a normal reference to a known 121/// object, return the Value for that object. 122static void getUnderlyingObjectsForInstr(const MachineInstr *MI, 123 const MachineFrameInfo *MFI, 124 SmallVectorImpl<std::pair<const Value *, bool> > &Objects) { 125 if (!MI->hasOneMemOperand() || 126 !(*MI->memoperands_begin())->getValue() || 127 (*MI->memoperands_begin())->isVolatile()) 128 return; 129 130 const Value *V = (*MI->memoperands_begin())->getValue(); 131 if (!V) 132 return; 133 134 SmallVector<Value *, 4> Objs; 135 getUnderlyingObjects(V, Objs); 136 137 for (SmallVector<Value *, 4>::iterator I = Objs.begin(), IE = Objs.end(); 138 I != IE; ++I) { 139 bool MayAlias = true; 140 V = *I; 141 142 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) { 143 // For now, ignore PseudoSourceValues which may alias LLVM IR values 144 // because the code that uses this function has no way to cope with 145 // such aliases. 146 147 if (PSV->isAliased(MFI)) { 148 Objects.clear(); 149 return; 150 } 151 152 MayAlias = PSV->mayAlias(MFI); 153 } else if (!isIdentifiedObject(V)) { 154 Objects.clear(); 155 return; 156 } 157 158 Objects.push_back(std::make_pair(V, MayAlias)); 159 } 160} 161 162void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) { 163 BB = bb; 164} 165 166void ScheduleDAGInstrs::finishBlock() { 167 // Subclasses should no longer refer to the old block. 168 BB = 0; 169} 170 171/// Initialize the map with the number of registers. 172void Reg2SUnitsMap::setRegLimit(unsigned Limit) { 173 PhysRegSet.setUniverse(Limit); 174 SUnits.resize(Limit); 175} 176 177/// Clear the map without deallocating storage. 178void Reg2SUnitsMap::clear() { 179 for (const_iterator I = reg_begin(), E = reg_end(); I != E; ++I) { 180 SUnits[*I].clear(); 181 } 182 PhysRegSet.clear(); 183} 184 185/// Initialize the DAG and common scheduler state for the current scheduling 186/// region. This does not actually create the DAG, only clears it. The 187/// scheduling driver may call BuildSchedGraph multiple times per scheduling 188/// region. 189void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb, 190 MachineBasicBlock::iterator begin, 191 MachineBasicBlock::iterator end, 192 unsigned endcount) { 193 assert(bb == BB && "startBlock should set BB"); 194 RegionBegin = begin; 195 RegionEnd = end; 196 EndIndex = endcount; 197 MISUnitMap.clear(); 198 199 ScheduleDAG::clearDAG(); 200} 201 202/// Close the current scheduling region. Don't clear any state in case the 203/// driver wants to refer to the previous scheduling region. 204void ScheduleDAGInstrs::exitRegion() { 205 // Nothing to do. 206} 207 208/// addSchedBarrierDeps - Add dependencies from instructions in the current 209/// list of instructions being scheduled to scheduling barrier by adding 210/// the exit SU to the register defs and use list. This is because we want to 211/// make sure instructions which define registers that are either used by 212/// the terminator or are live-out are properly scheduled. This is 213/// especially important when the definition latency of the return value(s) 214/// are too high to be hidden by the branch or when the liveout registers 215/// used by instructions in the fallthrough block. 216void ScheduleDAGInstrs::addSchedBarrierDeps() { 217 MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : 0; 218 ExitSU.setInstr(ExitMI); 219 bool AllDepKnown = ExitMI && 220 (ExitMI->isCall() || ExitMI->isBarrier()); 221 if (ExitMI && AllDepKnown) { 222 // If it's a call or a barrier, add dependencies on the defs and uses of 223 // instruction. 224 for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) { 225 const MachineOperand &MO = ExitMI->getOperand(i); 226 if (!MO.isReg() || MO.isDef()) continue; 227 unsigned Reg = MO.getReg(); 228 if (Reg == 0) continue; 229 230 if (TRI->isPhysicalRegister(Reg)) 231 Uses[Reg].push_back(PhysRegSUOper(&ExitSU, -1)); 232 else { 233 assert(!IsPostRA && "Virtual register encountered after regalloc."); 234 if (MO.readsReg()) // ignore undef operands 235 addVRegUseDeps(&ExitSU, i); 236 } 237 } 238 } else { 239 // For others, e.g. fallthrough, conditional branch, assume the exit 240 // uses all the registers that are livein to the successor blocks. 241 assert(Uses.empty() && "Uses in set before adding deps?"); 242 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), 243 SE = BB->succ_end(); SI != SE; ++SI) 244 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(), 245 E = (*SI)->livein_end(); I != E; ++I) { 246 unsigned Reg = *I; 247 if (!Uses.contains(Reg)) 248 Uses[Reg].push_back(PhysRegSUOper(&ExitSU, -1)); 249 } 250 } 251} 252 253/// MO is an operand of SU's instruction that defines a physical register. Add 254/// data dependencies from SU to any uses of the physical register. 255void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { 256 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); 257 assert(MO.isDef() && "expect physreg def"); 258 259 // Ask the target if address-backscheduling is desirable, and if so how much. 260 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>(); 261 262 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true); 263 Alias.isValid(); ++Alias) { 264 if (!Uses.contains(*Alias)) 265 continue; 266 std::vector<PhysRegSUOper> &UseList = Uses[*Alias]; 267 for (unsigned i = 0, e = UseList.size(); i != e; ++i) { 268 SUnit *UseSU = UseList[i].SU; 269 if (UseSU == SU) 270 continue; 271 272 // Adjust the dependence latency using operand def/use information, 273 // then allow the target to perform its own adjustments. 274 int UseOp = UseList[i].OpIdx; 275 MachineInstr *RegUse = 0; 276 SDep Dep; 277 if (UseOp < 0) 278 Dep = SDep(SU, SDep::Artificial); 279 else { 280 Dep = SDep(SU, SDep::Data, *Alias); 281 RegUse = UseSU->getInstr(); 282 Dep.setMinLatency( 283 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, 284 RegUse, UseOp, /*FindMin=*/true)); 285 } 286 Dep.setLatency( 287 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, 288 RegUse, UseOp, /*FindMin=*/false)); 289 290 ST.adjustSchedDependency(SU, UseSU, Dep); 291 UseSU->addPred(Dep); 292 } 293 } 294} 295 296/// addPhysRegDeps - Add register dependencies (data, anti, and output) from 297/// this SUnit to following instructions in the same scheduling region that 298/// depend the physical register referenced at OperIdx. 299void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) { 300 const MachineInstr *MI = SU->getInstr(); 301 const MachineOperand &MO = MI->getOperand(OperIdx); 302 303 // Optionally add output and anti dependencies. For anti 304 // dependencies we use a latency of 0 because for a multi-issue 305 // target we want to allow the defining instruction to issue 306 // in the same cycle as the using instruction. 307 // TODO: Using a latency of 1 here for output dependencies assumes 308 // there's no cost for reusing registers. 309 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output; 310 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true); 311 Alias.isValid(); ++Alias) { 312 if (!Defs.contains(*Alias)) 313 continue; 314 std::vector<PhysRegSUOper> &DefList = Defs[*Alias]; 315 for (unsigned i = 0, e = DefList.size(); i != e; ++i) { 316 SUnit *DefSU = DefList[i].SU; 317 if (DefSU == &ExitSU) 318 continue; 319 if (DefSU != SU && 320 (Kind != SDep::Output || !MO.isDead() || 321 !DefSU->getInstr()->registerDefIsDead(*Alias))) { 322 if (Kind == SDep::Anti) 323 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias)); 324 else { 325 SDep Dep(SU, Kind, /*Reg=*/*Alias); 326 unsigned OutLatency = 327 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()); 328 Dep.setMinLatency(OutLatency); 329 Dep.setLatency(OutLatency); 330 DefSU->addPred(Dep); 331 } 332 } 333 } 334 } 335 336 if (!MO.isDef()) { 337 // Either insert a new Reg2SUnits entry with an empty SUnits list, or 338 // retrieve the existing SUnits list for this register's uses. 339 // Push this SUnit on the use list. 340 Uses[MO.getReg()].push_back(PhysRegSUOper(SU, OperIdx)); 341 } 342 else { 343 addPhysRegDataDeps(SU, OperIdx); 344 345 // Either insert a new Reg2SUnits entry with an empty SUnits list, or 346 // retrieve the existing SUnits list for this register's defs. 347 std::vector<PhysRegSUOper> &DefList = Defs[MO.getReg()]; 348 349 // clear this register's use list 350 if (Uses.contains(MO.getReg())) 351 Uses[MO.getReg()].clear(); 352 353 if (!MO.isDead()) 354 DefList.clear(); 355 356 // Calls will not be reordered because of chain dependencies (see 357 // below). Since call operands are dead, calls may continue to be added 358 // to the DefList making dependence checking quadratic in the size of 359 // the block. Instead, we leave only one call at the back of the 360 // DefList. 361 if (SU->isCall) { 362 while (!DefList.empty() && DefList.back().SU->isCall) 363 DefList.pop_back(); 364 } 365 // Defs are pushed in the order they are visited and never reordered. 366 DefList.push_back(PhysRegSUOper(SU, OperIdx)); 367 } 368} 369 370/// addVRegDefDeps - Add register output and data dependencies from this SUnit 371/// to instructions that occur later in the same scheduling region if they read 372/// from or write to the virtual register defined at OperIdx. 373/// 374/// TODO: Hoist loop induction variable increments. This has to be 375/// reevaluated. Generally, IV scheduling should be done before coalescing. 376void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) { 377 const MachineInstr *MI = SU->getInstr(); 378 unsigned Reg = MI->getOperand(OperIdx).getReg(); 379 380 // Singly defined vregs do not have output/anti dependencies. 381 // The current operand is a def, so we have at least one. 382 // Check here if there are any others... 383 if (MRI.hasOneDef(Reg)) 384 return; 385 386 // Add output dependence to the next nearest def of this vreg. 387 // 388 // Unless this definition is dead, the output dependence should be 389 // transitively redundant with antidependencies from this definition's 390 // uses. We're conservative for now until we have a way to guarantee the uses 391 // are not eliminated sometime during scheduling. The output dependence edge 392 // is also useful if output latency exceeds def-use latency. 393 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg); 394 if (DefI == VRegDefs.end()) 395 VRegDefs.insert(VReg2SUnit(Reg, SU)); 396 else { 397 SUnit *DefSU = DefI->SU; 398 if (DefSU != SU && DefSU != &ExitSU) { 399 SDep Dep(SU, SDep::Output, Reg); 400 unsigned OutLatency = 401 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()); 402 Dep.setMinLatency(OutLatency); 403 Dep.setLatency(OutLatency); 404 DefSU->addPred(Dep); 405 } 406 DefI->SU = SU; 407 } 408} 409 410/// addVRegUseDeps - Add a register data dependency if the instruction that 411/// defines the virtual register used at OperIdx is mapped to an SUnit. Add a 412/// register antidependency from this SUnit to instructions that occur later in 413/// the same scheduling region if they write the virtual register. 414/// 415/// TODO: Handle ExitSU "uses" properly. 416void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) { 417 MachineInstr *MI = SU->getInstr(); 418 unsigned Reg = MI->getOperand(OperIdx).getReg(); 419 420 // Lookup this operand's reaching definition. 421 assert(LIS && "vreg dependencies requires LiveIntervals"); 422 LiveRangeQuery LRQ(LIS->getInterval(Reg), LIS->getInstructionIndex(MI)); 423 VNInfo *VNI = LRQ.valueIn(); 424 425 // VNI will be valid because MachineOperand::readsReg() is checked by caller. 426 assert(VNI && "No value to read by operand"); 427 MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def); 428 // Phis and other noninstructions (after coalescing) have a NULL Def. 429 if (Def) { 430 SUnit *DefSU = getSUnit(Def); 431 if (DefSU) { 432 // The reaching Def lives within this scheduling region. 433 // Create a data dependence. 434 SDep dep(DefSU, SDep::Data, Reg); 435 // Adjust the dependence latency using operand def/use information, then 436 // allow the target to perform its own adjustments. 437 int DefOp = Def->findRegisterDefOperandIdx(Reg); 438 dep.setLatency( 439 SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, false)); 440 dep.setMinLatency( 441 SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, true)); 442 443 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>(); 444 ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep)); 445 SU->addPred(dep); 446 } 447 } 448 449 // Add antidependence to the following def of the vreg it uses. 450 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg); 451 if (DefI != VRegDefs.end() && DefI->SU != SU) 452 DefI->SU->addPred(SDep(SU, SDep::Anti, Reg)); 453} 454 455/// Return true if MI is an instruction we are unable to reason about 456/// (like a call or something with unmodeled side effects). 457static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) { 458 if (MI->isCall() || MI->hasUnmodeledSideEffects() || 459 (MI->hasOrderedMemoryRef() && 460 (!MI->mayLoad() || !MI->isInvariantLoad(AA)))) 461 return true; 462 return false; 463} 464 465// This MI might have either incomplete info, or known to be unsafe 466// to deal with (i.e. volatile object). 467static inline bool isUnsafeMemoryObject(MachineInstr *MI, 468 const MachineFrameInfo *MFI) { 469 if (!MI || MI->memoperands_empty()) 470 return true; 471 // We purposefully do no check for hasOneMemOperand() here 472 // in hope to trigger an assert downstream in order to 473 // finish implementation. 474 if ((*MI->memoperands_begin())->isVolatile() || 475 MI->hasUnmodeledSideEffects()) 476 return true; 477 const Value *V = (*MI->memoperands_begin())->getValue(); 478 if (!V) 479 return true; 480 481 SmallVector<Value *, 4> Objs; 482 getUnderlyingObjects(V, Objs); 483 for (SmallVector<Value *, 4>::iterator I = Objs.begin(), 484 IE = Objs.end(); I != IE; ++I) { 485 V = *I; 486 487 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) { 488 // Similarly to getUnderlyingObjectForInstr: 489 // For now, ignore PseudoSourceValues which may alias LLVM IR values 490 // because the code that uses this function has no way to cope with 491 // such aliases. 492 if (PSV->isAliased(MFI)) 493 return true; 494 } 495 496 // Does this pointer refer to a distinct and identifiable object? 497 if (!isIdentifiedObject(V)) 498 return true; 499 } 500 501 return false; 502} 503 504/// This returns true if the two MIs need a chain edge betwee them. 505/// If these are not even memory operations, we still may need 506/// chain deps between them. The question really is - could 507/// these two MIs be reordered during scheduling from memory dependency 508/// point of view. 509static bool MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI, 510 MachineInstr *MIa, 511 MachineInstr *MIb) { 512 // Cover a trivial case - no edge is need to itself. 513 if (MIa == MIb) 514 return false; 515 516 if (isUnsafeMemoryObject(MIa, MFI) || isUnsafeMemoryObject(MIb, MFI)) 517 return true; 518 519 // If we are dealing with two "normal" loads, we do not need an edge 520 // between them - they could be reordered. 521 if (!MIa->mayStore() && !MIb->mayStore()) 522 return false; 523 524 // To this point analysis is generic. From here on we do need AA. 525 if (!AA) 526 return true; 527 528 MachineMemOperand *MMOa = *MIa->memoperands_begin(); 529 MachineMemOperand *MMOb = *MIb->memoperands_begin(); 530 531 // FIXME: Need to handle multiple memory operands to support all targets. 532 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand()) 533 llvm_unreachable("Multiple memory operands."); 534 535 // The following interface to AA is fashioned after DAGCombiner::isAlias 536 // and operates with MachineMemOperand offset with some important 537 // assumptions: 538 // - LLVM fundamentally assumes flat address spaces. 539 // - MachineOperand offset can *only* result from legalization and 540 // cannot affect queries other than the trivial case of overlap 541 // checking. 542 // - These offsets never wrap and never step outside 543 // of allocated objects. 544 // - There should never be any negative offsets here. 545 // 546 // FIXME: Modify API to hide this math from "user" 547 // FIXME: Even before we go to AA we can reason locally about some 548 // memory objects. It can save compile time, and possibly catch some 549 // corner cases not currently covered. 550 551 assert ((MMOa->getOffset() >= 0) && "Negative MachineMemOperand offset"); 552 assert ((MMOb->getOffset() >= 0) && "Negative MachineMemOperand offset"); 553 554 int64_t MinOffset = std::min(MMOa->getOffset(), MMOb->getOffset()); 555 int64_t Overlapa = MMOa->getSize() + MMOa->getOffset() - MinOffset; 556 int64_t Overlapb = MMOb->getSize() + MMOb->getOffset() - MinOffset; 557 558 AliasAnalysis::AliasResult AAResult = AA->alias( 559 AliasAnalysis::Location(MMOa->getValue(), Overlapa, 560 MMOa->getTBAAInfo()), 561 AliasAnalysis::Location(MMOb->getValue(), Overlapb, 562 MMOb->getTBAAInfo())); 563 564 return (AAResult != AliasAnalysis::NoAlias); 565} 566 567/// This recursive function iterates over chain deps of SUb looking for 568/// "latest" node that needs a chain edge to SUa. 569static unsigned 570iterateChainSucc(AliasAnalysis *AA, const MachineFrameInfo *MFI, 571 SUnit *SUa, SUnit *SUb, SUnit *ExitSU, unsigned *Depth, 572 SmallPtrSet<const SUnit*, 16> &Visited) { 573 if (!SUa || !SUb || SUb == ExitSU) 574 return *Depth; 575 576 // Remember visited nodes. 577 if (!Visited.insert(SUb)) 578 return *Depth; 579 // If there is _some_ dependency already in place, do not 580 // descend any further. 581 // TODO: Need to make sure that if that dependency got eliminated or ignored 582 // for any reason in the future, we would not violate DAG topology. 583 // Currently it does not happen, but makes an implicit assumption about 584 // future implementation. 585 // 586 // Independently, if we encounter node that is some sort of global 587 // object (like a call) we already have full set of dependencies to it 588 // and we can stop descending. 589 if (SUa->isSucc(SUb) || 590 isGlobalMemoryObject(AA, SUb->getInstr())) 591 return *Depth; 592 593 // If we do need an edge, or we have exceeded depth budget, 594 // add that edge to the predecessors chain of SUb, 595 // and stop descending. 596 if (*Depth > 200 || 597 MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) { 598 SUb->addPred(SDep(SUa, SDep::MayAliasMem)); 599 return *Depth; 600 } 601 // Track current depth. 602 (*Depth)++; 603 // Iterate over chain dependencies only. 604 for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E = SUb->Succs.end(); 605 I != E; ++I) 606 if (I->isCtrl()) 607 iterateChainSucc (AA, MFI, SUa, I->getSUnit(), ExitSU, Depth, Visited); 608 return *Depth; 609} 610 611/// This function assumes that "downward" from SU there exist 612/// tail/leaf of already constructed DAG. It iterates downward and 613/// checks whether SU can be aliasing any node dominated 614/// by it. 615static void adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI, 616 SUnit *SU, SUnit *ExitSU, std::set<SUnit *> &CheckList, 617 unsigned LatencyToLoad) { 618 if (!SU) 619 return; 620 621 SmallPtrSet<const SUnit*, 16> Visited; 622 unsigned Depth = 0; 623 624 for (std::set<SUnit *>::iterator I = CheckList.begin(), IE = CheckList.end(); 625 I != IE; ++I) { 626 if (SU == *I) 627 continue; 628 if (MIsNeedChainEdge(AA, MFI, SU->getInstr(), (*I)->getInstr())) { 629 SDep Dep(SU, SDep::MayAliasMem); 630 Dep.setLatency(((*I)->getInstr()->mayLoad()) ? LatencyToLoad : 0); 631 (*I)->addPred(Dep); 632 } 633 // Now go through all the chain successors and iterate from them. 634 // Keep track of visited nodes. 635 for (SUnit::const_succ_iterator J = (*I)->Succs.begin(), 636 JE = (*I)->Succs.end(); J != JE; ++J) 637 if (J->isCtrl()) 638 iterateChainSucc (AA, MFI, SU, J->getSUnit(), 639 ExitSU, &Depth, Visited); 640 } 641} 642 643/// Check whether two objects need a chain edge, if so, add it 644/// otherwise remember the rejected SU. 645static inline 646void addChainDependency (AliasAnalysis *AA, const MachineFrameInfo *MFI, 647 SUnit *SUa, SUnit *SUb, 648 std::set<SUnit *> &RejectList, 649 unsigned TrueMemOrderLatency = 0, 650 bool isNormalMemory = false) { 651 // If this is a false dependency, 652 // do not add the edge, but rememeber the rejected node. 653 if (!EnableAASchedMI || 654 MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) { 655 SDep Dep(SUa, isNormalMemory ? SDep::MayAliasMem : SDep::Barrier); 656 Dep.setLatency(TrueMemOrderLatency); 657 SUb->addPred(Dep); 658 } 659 else { 660 // Duplicate entries should be ignored. 661 RejectList.insert(SUb); 662 DEBUG(dbgs() << "\tReject chain dep between SU(" 663 << SUa->NodeNum << ") and SU(" 664 << SUb->NodeNum << ")\n"); 665 } 666} 667 668/// Create an SUnit for each real instruction, numbered in top-down toplological 669/// order. The instruction order A < B, implies that no edge exists from B to A. 670/// 671/// Map each real instruction to its SUnit. 672/// 673/// After initSUnits, the SUnits vector cannot be resized and the scheduler may 674/// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs 675/// instead of pointers. 676/// 677/// MachineScheduler relies on initSUnits numbering the nodes by their order in 678/// the original instruction list. 679void ScheduleDAGInstrs::initSUnits() { 680 // We'll be allocating one SUnit for each real instruction in the region, 681 // which is contained within a basic block. 682 SUnits.reserve(BB->size()); 683 684 for (MachineBasicBlock::iterator I = RegionBegin; I != RegionEnd; ++I) { 685 MachineInstr *MI = I; 686 if (MI->isDebugValue()) 687 continue; 688 689 SUnit *SU = newSUnit(MI); 690 MISUnitMap[MI] = SU; 691 692 SU->isCall = MI->isCall(); 693 SU->isCommutable = MI->isCommutable(); 694 695 // Assign the Latency field of SU using target-provided information. 696 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr()); 697 } 698} 699 700/// If RegPressure is non null, compute register pressure as a side effect. The 701/// DAG builder is an efficient place to do it because it already visits 702/// operands. 703void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA, 704 RegPressureTracker *RPTracker) { 705 // Create an SUnit for each real instruction. 706 initSUnits(); 707 708 // We build scheduling units by walking a block's instruction list from bottom 709 // to top. 710 711 // Remember where a generic side-effecting instruction is as we procede. 712 SUnit *BarrierChain = 0, *AliasChain = 0; 713 714 // Memory references to specific known memory locations are tracked 715 // so that they can be given more precise dependencies. We track 716 // separately the known memory locations that may alias and those 717 // that are known not to alias 718 MapVector<const Value *, SUnit *> AliasMemDefs, NonAliasMemDefs; 719 MapVector<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses; 720 std::set<SUnit*> RejectMemNodes; 721 722 // Remove any stale debug info; sometimes BuildSchedGraph is called again 723 // without emitting the info from the previous call. 724 DbgValues.clear(); 725 FirstDbgValue = NULL; 726 727 assert(Defs.empty() && Uses.empty() && 728 "Only BuildGraph should update Defs/Uses"); 729 Defs.setRegLimit(TRI->getNumRegs()); 730 Uses.setRegLimit(TRI->getNumRegs()); 731 732 assert(VRegDefs.empty() && "Only BuildSchedGraph may access VRegDefs"); 733 // FIXME: Allow SparseSet to reserve space for the creation of virtual 734 // registers during scheduling. Don't artificially inflate the Universe 735 // because we want to assert that vregs are not created during DAG building. 736 VRegDefs.setUniverse(MRI.getNumVirtRegs()); 737 738 // Model data dependencies between instructions being scheduled and the 739 // ExitSU. 740 addSchedBarrierDeps(); 741 742 // Walk the list of instructions, from bottom moving up. 743 MachineInstr *DbgMI = NULL; 744 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin; 745 MII != MIE; --MII) { 746 MachineInstr *MI = prior(MII); 747 if (MI && DbgMI) { 748 DbgValues.push_back(std::make_pair(DbgMI, MI)); 749 DbgMI = NULL; 750 } 751 752 if (MI->isDebugValue()) { 753 DbgMI = MI; 754 continue; 755 } 756 if (RPTracker) { 757 RPTracker->recede(); 758 assert(RPTracker->getPos() == prior(MII) && "RPTracker can't find MI"); 759 } 760 761 assert((!MI->isTerminator() || CanHandleTerminators) && !MI->isLabel() && 762 "Cannot schedule terminators or labels!"); 763 764 SUnit *SU = MISUnitMap[MI]; 765 assert(SU && "No SUnit mapped to this MI"); 766 767 // Add register-based dependencies (data, anti, and output). 768 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) { 769 const MachineOperand &MO = MI->getOperand(j); 770 if (!MO.isReg()) continue; 771 unsigned Reg = MO.getReg(); 772 if (Reg == 0) continue; 773 774 if (TRI->isPhysicalRegister(Reg)) 775 addPhysRegDeps(SU, j); 776 else { 777 assert(!IsPostRA && "Virtual register encountered!"); 778 if (MO.isDef()) 779 addVRegDefDeps(SU, j); 780 else if (MO.readsReg()) // ignore undef operands 781 addVRegUseDeps(SU, j); 782 } 783 } 784 785 // Add chain dependencies. 786 // Chain dependencies used to enforce memory order should have 787 // latency of 0 (except for true dependency of Store followed by 788 // aliased Load... we estimate that with a single cycle of latency 789 // assuming the hardware will bypass) 790 // Note that isStoreToStackSlot and isLoadFromStackSLot are not usable 791 // after stack slots are lowered to actual addresses. 792 // TODO: Use an AliasAnalysis and do real alias-analysis queries, and 793 // produce more precise dependence information. 794 unsigned TrueMemOrderLatency = MI->mayStore() ? 1 : 0; 795 if (isGlobalMemoryObject(AA, MI)) { 796 // Be conservative with these and add dependencies on all memory 797 // references, even those that are known to not alias. 798 for (MapVector<const Value *, SUnit *>::iterator I = 799 NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) { 800 I->second->addPred(SDep(SU, SDep::Barrier)); 801 } 802 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I = 803 NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) { 804 for (unsigned i = 0, e = I->second.size(); i != e; ++i) { 805 SDep Dep(SU, SDep::Barrier); 806 Dep.setLatency(TrueMemOrderLatency); 807 I->second[i]->addPred(Dep); 808 } 809 } 810 // Add SU to the barrier chain. 811 if (BarrierChain) 812 BarrierChain->addPred(SDep(SU, SDep::Barrier)); 813 BarrierChain = SU; 814 // This is a barrier event that acts as a pivotal node in the DAG, 815 // so it is safe to clear list of exposed nodes. 816 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, 817 TrueMemOrderLatency); 818 RejectMemNodes.clear(); 819 NonAliasMemDefs.clear(); 820 NonAliasMemUses.clear(); 821 822 // fall-through 823 new_alias_chain: 824 // Chain all possibly aliasing memory references though SU. 825 if (AliasChain) { 826 unsigned ChainLatency = 0; 827 if (AliasChain->getInstr()->mayLoad()) 828 ChainLatency = TrueMemOrderLatency; 829 addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes, 830 ChainLatency); 831 } 832 AliasChain = SU; 833 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k) 834 addChainDependency(AA, MFI, SU, PendingLoads[k], RejectMemNodes, 835 TrueMemOrderLatency); 836 for (MapVector<const Value *, SUnit *>::iterator I = AliasMemDefs.begin(), 837 E = AliasMemDefs.end(); I != E; ++I) 838 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes); 839 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I = 840 AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) { 841 for (unsigned i = 0, e = I->second.size(); i != e; ++i) 842 addChainDependency(AA, MFI, SU, I->second[i], RejectMemNodes, 843 TrueMemOrderLatency); 844 } 845 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, 846 TrueMemOrderLatency); 847 PendingLoads.clear(); 848 AliasMemDefs.clear(); 849 AliasMemUses.clear(); 850 } else if (MI->mayStore()) { 851 SmallVector<std::pair<const Value *, bool>, 4> Objs; 852 getUnderlyingObjectsForInstr(MI, MFI, Objs); 853 854 if (Objs.empty()) { 855 // Treat all other stores conservatively. 856 goto new_alias_chain; 857 } 858 859 bool MayAlias = false; 860 for (SmallVector<std::pair<const Value *, bool>, 4>::iterator 861 K = Objs.begin(), KE = Objs.end(); K != KE; ++K) { 862 const Value *V = K->first; 863 bool ThisMayAlias = K->second; 864 if (ThisMayAlias) 865 MayAlias = true; 866 867 // A store to a specific PseudoSourceValue. Add precise dependencies. 868 // Record the def in MemDefs, first adding a dep if there is 869 // an existing def. 870 MapVector<const Value *, SUnit *>::iterator I = 871 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V)); 872 MapVector<const Value *, SUnit *>::iterator IE = 873 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end()); 874 if (I != IE) { 875 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes, 0, true); 876 I->second = SU; 877 } else { 878 if (ThisMayAlias) 879 AliasMemDefs[V] = SU; 880 else 881 NonAliasMemDefs[V] = SU; 882 } 883 // Handle the uses in MemUses, if there are any. 884 MapVector<const Value *, std::vector<SUnit *> >::iterator J = 885 ((ThisMayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V)); 886 MapVector<const Value *, std::vector<SUnit *> >::iterator JE = 887 ((ThisMayAlias) ? AliasMemUses.end() : NonAliasMemUses.end()); 888 if (J != JE) { 889 for (unsigned i = 0, e = J->second.size(); i != e; ++i) 890 addChainDependency(AA, MFI, SU, J->second[i], RejectMemNodes, 891 TrueMemOrderLatency, true); 892 J->second.clear(); 893 } 894 } 895 if (MayAlias) { 896 // Add dependencies from all the PendingLoads, i.e. loads 897 // with no underlying object. 898 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k) 899 addChainDependency(AA, MFI, SU, PendingLoads[k], RejectMemNodes, 900 TrueMemOrderLatency); 901 // Add dependence on alias chain, if needed. 902 if (AliasChain) 903 addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes); 904 // But we also should check dependent instructions for the 905 // SU in question. 906 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, 907 TrueMemOrderLatency); 908 } 909 // Add dependence on barrier chain, if needed. 910 // There is no point to check aliasing on barrier event. Even if 911 // SU and barrier _could_ be reordered, they should not. In addition, 912 // we have lost all RejectMemNodes below barrier. 913 if (BarrierChain) 914 BarrierChain->addPred(SDep(SU, SDep::Barrier)); 915 916 if (!ExitSU.isPred(SU)) 917 // Push store's up a bit to avoid them getting in between cmp 918 // and branches. 919 ExitSU.addPred(SDep(SU, SDep::Artificial)); 920 } else if (MI->mayLoad()) { 921 bool MayAlias = true; 922 if (MI->isInvariantLoad(AA)) { 923 // Invariant load, no chain dependencies needed! 924 } else { 925 SmallVector<std::pair<const Value *, bool>, 4> Objs; 926 getUnderlyingObjectsForInstr(MI, MFI, Objs); 927 928 if (Objs.empty()) { 929 // A load with no underlying object. Depend on all 930 // potentially aliasing stores. 931 for (MapVector<const Value *, SUnit *>::iterator I = 932 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I) 933 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes); 934 935 PendingLoads.push_back(SU); 936 MayAlias = true; 937 } else { 938 MayAlias = false; 939 } 940 941 for (SmallVector<std::pair<const Value *, bool>, 4>::iterator 942 J = Objs.begin(), JE = Objs.end(); J != JE; ++J) { 943 const Value *V = J->first; 944 bool ThisMayAlias = J->second; 945 946 if (ThisMayAlias) 947 MayAlias = true; 948 949 // A load from a specific PseudoSourceValue. Add precise dependencies. 950 MapVector<const Value *, SUnit *>::iterator I = 951 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V)); 952 MapVector<const Value *, SUnit *>::iterator IE = 953 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end()); 954 if (I != IE) 955 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes, 0, true); 956 if (ThisMayAlias) 957 AliasMemUses[V].push_back(SU); 958 else 959 NonAliasMemUses[V].push_back(SU); 960 } 961 if (MayAlias) 962 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, /*Latency=*/0); 963 // Add dependencies on alias and barrier chains, if needed. 964 if (MayAlias && AliasChain) 965 addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes); 966 if (BarrierChain) 967 BarrierChain->addPred(SDep(SU, SDep::Barrier)); 968 } 969 } 970 } 971 if (DbgMI) 972 FirstDbgValue = DbgMI; 973 974 Defs.clear(); 975 Uses.clear(); 976 VRegDefs.clear(); 977 PendingLoads.clear(); 978} 979 980void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const { 981#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 982 SU->getInstr()->dump(); 983#endif 984} 985 986std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const { 987 std::string s; 988 raw_string_ostream oss(s); 989 if (SU == &EntrySU) 990 oss << "<entry>"; 991 else if (SU == &ExitSU) 992 oss << "<exit>"; 993 else 994 SU->getInstr()->print(oss); 995 return oss.str(); 996} 997 998/// Return the basic block label. It is not necessarilly unique because a block 999/// contains multiple scheduling regions. But it is fine for visualization. 1000std::string ScheduleDAGInstrs::getDAGName() const { 1001 return "dag." + BB->getFullName(); 1002} 1003 1004//===----------------------------------------------------------------------===// 1005// SchedDFSResult Implementation 1006//===----------------------------------------------------------------------===// 1007 1008namespace llvm { 1009/// \brief Internal state used to compute SchedDFSResult. 1010class SchedDFSImpl { 1011 SchedDFSResult &R; 1012 1013 /// Join DAG nodes into equivalence classes by their subtree. 1014 IntEqClasses SubtreeClasses; 1015 /// List PredSU, SuccSU pairs that represent data edges between subtrees. 1016 std::vector<std::pair<const SUnit*, const SUnit*> > ConnectionPairs; 1017 1018public: 1019 SchedDFSImpl(SchedDFSResult &r): R(r), SubtreeClasses(R.DFSData.size()) {} 1020 1021 /// SubtreID is initialized to zero, set to itself to flag the root of a 1022 /// subtree, set to the parent to indicate an interior node, 1023 /// then set to a representative subtree ID during finalization. 1024 bool isVisited(const SUnit *SU) const { 1025 return R.DFSData[SU->NodeNum].SubtreeID; 1026 } 1027 1028 /// Initialize this node's instruction count. We don't need to flag the node 1029 /// visited until visitPostorder because the DAG cannot have cycles. 1030 void visitPreorder(const SUnit *SU) { 1031 R.DFSData[SU->NodeNum].InstrCount = SU->getInstr()->isTransient() ? 0 : 1; 1032 } 1033 1034 /// Mark this node as either the root of a subtree or an interior 1035 /// node. Increment the parent node's instruction count. 1036 void visitPostorder(const SUnit *SU, const SDep *PredDep, const SUnit *Parent) { 1037 R.DFSData[SU->NodeNum].SubtreeID = SU->NodeNum; 1038 1039 // Join the child to its parent if they are connected via data dependence 1040 // and do not exceed the limit. 1041 if (!Parent || PredDep->getKind() != SDep::Data) 1042 return; 1043 1044 unsigned PredCnt = R.DFSData[SU->NodeNum].InstrCount; 1045 if (PredCnt > R.SubtreeLimit) 1046 return; 1047 1048 R.DFSData[SU->NodeNum].SubtreeID = Parent->NodeNum; 1049 1050 // Add the recently finished predecessor's bottom-up descendent count. 1051 R.DFSData[Parent->NodeNum].InstrCount += PredCnt; 1052 SubtreeClasses.join(Parent->NodeNum, SU->NodeNum); 1053 } 1054 1055 /// Determine whether the DFS cross edge should be considered a subtree edge 1056 /// or a connection between subtrees. 1057 void visitCross(const SDep &PredDep, const SUnit *Succ) { 1058 if (PredDep.getKind() == SDep::Data) { 1059 // If this is a cross edge to a root, join the subtrees. This happens when 1060 // the root was first reached by a non-data dependence. 1061 unsigned NodeNum = PredDep.getSUnit()->NodeNum; 1062 unsigned PredCnt = R.DFSData[NodeNum].InstrCount; 1063 if (R.DFSData[NodeNum].SubtreeID == NodeNum && PredCnt < R.SubtreeLimit) { 1064 R.DFSData[NodeNum].SubtreeID = Succ->NodeNum; 1065 R.DFSData[Succ->NodeNum].InstrCount += PredCnt; 1066 SubtreeClasses.join(Succ->NodeNum, NodeNum); 1067 return; 1068 } 1069 } 1070 ConnectionPairs.push_back(std::make_pair(PredDep.getSUnit(), Succ)); 1071 } 1072 1073 /// Set each node's subtree ID to the representative ID and record connections 1074 /// between trees. 1075 void finalize() { 1076 SubtreeClasses.compress(); 1077 R.SubtreeConnections.resize(SubtreeClasses.getNumClasses()); 1078 R.SubtreeConnectLevels.resize(SubtreeClasses.getNumClasses()); 1079 DEBUG(dbgs() << R.getNumSubtrees() << " subtrees:\n"); 1080 for (unsigned Idx = 0, End = R.DFSData.size(); Idx != End; ++Idx) { 1081 R.DFSData[Idx].SubtreeID = SubtreeClasses[Idx]; 1082 DEBUG(dbgs() << " SU(" << Idx << ") in tree " 1083 << R.DFSData[Idx].SubtreeID << '\n'); 1084 } 1085 for (std::vector<std::pair<const SUnit*, const SUnit*> >::const_iterator 1086 I = ConnectionPairs.begin(), E = ConnectionPairs.end(); 1087 I != E; ++I) { 1088 unsigned PredTree = SubtreeClasses[I->first->NodeNum]; 1089 unsigned SuccTree = SubtreeClasses[I->second->NodeNum]; 1090 if (PredTree == SuccTree) 1091 continue; 1092 unsigned Depth = I->first->getDepth(); 1093 addConnection(PredTree, SuccTree, Depth); 1094 addConnection(SuccTree, PredTree, Depth); 1095 } 1096 } 1097 1098protected: 1099 /// Called by finalize() to record a connection between trees. 1100 void addConnection(unsigned FromTree, unsigned ToTree, unsigned Depth) { 1101 if (!Depth) 1102 return; 1103 1104 SmallVectorImpl<SchedDFSResult::Connection> &Connections = 1105 R.SubtreeConnections[FromTree]; 1106 for (SmallVectorImpl<SchedDFSResult::Connection>::iterator 1107 I = Connections.begin(), E = Connections.end(); I != E; ++I) { 1108 if (I->TreeID == ToTree) { 1109 I->Level = std::max(I->Level, Depth); 1110 return; 1111 } 1112 } 1113 Connections.push_back(SchedDFSResult::Connection(ToTree, Depth)); 1114 } 1115}; 1116} // namespace llvm 1117 1118namespace { 1119/// \brief Manage the stack used by a reverse depth-first search over the DAG. 1120class SchedDAGReverseDFS { 1121 std::vector<std::pair<const SUnit*, SUnit::const_pred_iterator> > DFSStack; 1122public: 1123 bool isComplete() const { return DFSStack.empty(); } 1124 1125 void follow(const SUnit *SU) { 1126 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin())); 1127 } 1128 void advance() { ++DFSStack.back().second; } 1129 1130 const SDep *backtrack() { 1131 DFSStack.pop_back(); 1132 return DFSStack.empty() ? 0 : llvm::prior(DFSStack.back().second); 1133 } 1134 1135 const SUnit *getCurr() const { return DFSStack.back().first; } 1136 1137 SUnit::const_pred_iterator getPred() const { return DFSStack.back().second; } 1138 1139 SUnit::const_pred_iterator getPredEnd() const { 1140 return getCurr()->Preds.end(); 1141 } 1142}; 1143} // anonymous 1144 1145/// Compute an ILP metric for all nodes in the subDAG reachable via depth-first 1146/// search from this root. 1147void SchedDFSResult::compute(ArrayRef<SUnit *> Roots) { 1148 if (!IsBottomUp) 1149 llvm_unreachable("Top-down ILP metric is unimplemnted"); 1150 1151 SchedDFSImpl Impl(*this); 1152 for (ArrayRef<const SUnit*>::const_iterator 1153 RootI = Roots.begin(), RootE = Roots.end(); RootI != RootE; ++RootI) { 1154 SchedDAGReverseDFS DFS; 1155 Impl.visitPreorder(*RootI); 1156 DFS.follow(*RootI); 1157 for (;;) { 1158 // Traverse the leftmost path as far as possible. 1159 while (DFS.getPred() != DFS.getPredEnd()) { 1160 const SDep &PredDep = *DFS.getPred(); 1161 DFS.advance(); 1162 // If the pred is already valid, skip it. We may preorder visit a node 1163 // with InstrCount==0 more than once, but it won't affect heuristics 1164 // because we don't care about cross edges to leaf copies. 1165 if (Impl.isVisited(PredDep.getSUnit())) { 1166 Impl.visitCross(PredDep, DFS.getCurr()); 1167 continue; 1168 } 1169 Impl.visitPreorder(PredDep.getSUnit()); 1170 DFS.follow(PredDep.getSUnit()); 1171 } 1172 // Visit the top of the stack in postorder and backtrack. 1173 const SUnit *Child = DFS.getCurr(); 1174 const SDep *PredDep = DFS.backtrack(); 1175 Impl.visitPostorder(Child, PredDep, PredDep ? DFS.getCurr() : 0); 1176 if (DFS.isComplete()) 1177 break; 1178 } 1179 } 1180 Impl.finalize(); 1181} 1182 1183/// The root of the given SubtreeID was just scheduled. For all subtrees 1184/// connected to this tree, record the depth of the connection so that the 1185/// nearest connected subtrees can be prioritized. 1186void SchedDFSResult::scheduleTree(unsigned SubtreeID) { 1187 for (SmallVectorImpl<Connection>::const_iterator 1188 I = SubtreeConnections[SubtreeID].begin(), 1189 E = SubtreeConnections[SubtreeID].end(); I != E; ++I) { 1190 SubtreeConnectLevels[I->TreeID] = 1191 std::max(SubtreeConnectLevels[I->TreeID], I->Level); 1192 DEBUG(dbgs() << " Tree: " << I->TreeID 1193 << " @" << SubtreeConnectLevels[I->TreeID] << '\n'); 1194 } 1195} 1196 1197#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 1198void ILPValue::print(raw_ostream &OS) const { 1199 OS << InstrCount << " / " << Length << " = "; 1200 if (!Length) 1201 OS << "BADILP"; 1202 else 1203 OS << format("%g", ((double)InstrCount / Length)); 1204} 1205 1206void ILPValue::dump() const { 1207 dbgs() << *this << '\n'; 1208} 1209 1210namespace llvm { 1211 1212raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val) { 1213 Val.print(OS); 1214 return OS; 1215} 1216 1217} // namespace llvm 1218#endif // !NDEBUG || LLVM_ENABLE_DUMP 1219