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Searched defs:Op0IsKill (Results 1 - 7 of 7) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A D	FastISel.cpp	366 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 381 Op0IsKill, Imm, VT.getSimpleVT()); 392 ISDOpcode, Op0, Op0IsKill, CF); 410 Op0, Op0IsKill, 724 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 742 ISD::BITCAST, Op0, Op0IsKill); 1016 unsigned /Op0/, bool /Op0IsKill/) { 1022 unsigned /Op0/, bool /Op0IsKill/, 1038 unsigned /Op0/, bool /Op0IsKill/, 1045 unsigned /Op0/, bool /Op0IsKill/, 1062 FastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t Imm, MVT ImmType) argument 1111 FastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill) argument 1130 FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 1151 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument 1175 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 1196 FastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, uint64_t Imm1, uint64_t Imm2) argument 1219 FastEmitInst_rf(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, const ConstantFP FPImm) argument 1240 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument 1297 FastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill, uint32_t Idx) argument 1311 FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) argument [all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A D	FastISel.cpp	428 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 449 Op0IsKill, Imm, VT.getSimpleVT()); 461 ISDOpcode, Op0, Op0IsKill, CF); 476 ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill); 1301 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 1318 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill); 1702 bool /Op0IsKill/) { 1707 bool /Op0IsKill/, unsigned /Op1/, 1722 bool /Op0IsKill/, uint64_t /Imm/) { 1727 bool /Op0IsKill/, 1742 fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t Imm, MVT ImmType) argument 1815 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill) argument 1836 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 1860 fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument 1888 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 1910 fastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, uint64_t Imm1, uint64_t Imm2) argument 1954 fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument 1996 fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill, uint32_t Idx) argument 2010 fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) argument [all...]
/external/llvm/lib/Target/Mips/
H A D	MipsFastISel.cpp	180 unsigned Op0, bool Op0IsKill, 187 unsigned Op0, bool Op0IsKill, uint64_t imm1, 1868 unsigned Op0, bool Op0IsKill, 1882 .addReg(Op0, getKillRegState(Op0IsKill)) 1889 return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1, 186 fastEmitInst_riir(uint64_t inst, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, uint64_t imm1, uint64_t imm2, unsigned Op3, bool Op3IsKill) argument 1866 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
/external/llvm/lib/Target/PowerPC/
H A D	PPCFastISel.cpp	117 unsigned Op0, bool Op0IsKill, 121 unsigned Op0, bool Op0IsKill); 124 unsigned Op0, bool Op0IsKill, 2304 unsigned Op0, bool Op0IsKill, 2316 Op0, Op0IsKill, Imm); 2324 unsigned Op0, bool Op0IsKill) { 2329 return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill); 2337 unsigned Op0, bool Op0IsKill, 2343 return FastISel::fastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op0IsKill, 2302 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 2322 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill) argument 2335 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass* RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A D	ARMFastISel.cpp	113 unsigned Op0, bool Op0IsKill); 116 unsigned Op0, bool Op0IsKill, 120 unsigned Op0, bool Op0IsKill, 125 unsigned Op0, bool Op0IsKill, 129 unsigned Op0, bool Op0IsKill, 133 unsigned Op0, bool Op0IsKill, 144 unsigned Op0, bool Op0IsKill, 289 unsigned Op0, bool Op0IsKill) { 295 .addReg(Op0, Op0IsKill * RegState::Kill)); 298 .addReg(Op0, Op0IsKill * RegStat 287 FastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill) argument 306 FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 328 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument 353 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 375 FastEmitInst_rf(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, const ConstantFP FPImm) argument 397 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument 461 FastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill, uint32_t Idx) argument [all...]
/external/llvm/lib/Target/ARM/
H A D	ARMFastISel.cpp	106 unsigned Op0, bool Op0IsKill); 109 unsigned Op0, bool Op0IsKill, 113 unsigned Op0, bool Op0IsKill, 117 unsigned Op0, bool Op0IsKill, 280 unsigned Op0, bool Op0IsKill) { 289 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); 292 .addReg(Op0, Op0IsKill * RegState::Kill)); 302 unsigned Op0, bool Op0IsKill, 315 .addReg(Op0, Op0IsKill * RegState::Kill) 319 .addReg(Op0, Op0IsKill * RegStat 278 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill) argument 300 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 328 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 354 fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument [all...]
/external/llvm/lib/Target/AArch64/
H A D	AArch64FastISel.cpp	193 unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm); 211 unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, 213 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, 215 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, 217 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, 219 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill, 221 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, 223 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill, 225 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, 227 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill, 1478 emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm) argument 3868 emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 3888 emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 3898 emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 3908 emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, unsigned Op1Reg, bool Op1IsKill) argument 3934 emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument 4014 emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, unsigned Op1Reg, bool Op1IsKill) argument 4041 emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument 4135 emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, unsigned Op1Reg, bool Op1IsKill) argument 4162 emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument [all...]

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