Searched defs:RS (Results 26 - 50 of 55) sorted by relevance

123

/external/clang/lib/StaticAnalyzer/Core/
H A DRangeConstraintManager.cpp82 RangeSet(PrimRangeSet RS) : ranges(RS) {} argument
84 /// Create a new set with all ranges of this set and RS.
86 RangeSet addRange(Factory &F, const RangeSet &RS) { argument
87 PrimRangeSet Ranges(RS.ranges);
353 RangeSet getSymLERange(const RangeSet &RS, const llvm::APSInt &Int,
593 RangeConstraintManager::getSymLERange(const RangeSet &RS, argument
604 return RS;
611 return RS;
617 return RS
[all...]
H A DExprEngineCallAndReturn.cpp248 if (const ReturnStmt *RS = dyn_cast_or_null<ReturnStmt>(LastSt)) {
250 SVal V = state->getSVal(RS, LCtx);
979 void ExprEngine::VisitReturnStmt(const ReturnStmt *RS, ExplodedNode *Pred, argument
982 getCheckerManager().runCheckersForPreStmt(dstPreVisit, Pred, RS, *this);
986 if (RS->getRetValue()) {
989 B.generateNode(RS, *it, (*it)->getState());
/external/aac/libAACenc/src/
H A Dmetadata_compressor.cpp121 RS = 5, enumerator in enum:__anon282
531 drcComp->channelIdx[RS] = channelMapping.elInfo[2].ChannelIndex[1];
539 drcComp->channelIdx[RS] = channelMapping.elInfo[2].ChannelIndex[1];
548 drcComp->channelIdx[RS] = channelMapping.elInfo[3].ChannelIndex[1]; /* rs */
558 drcComp->channelIdx[RS] = channelMapping.elInfo[3].ChannelIndex[1]; /* rrear */
895 if (drcComp->channelIdx[RS] >= 0) tmp -= fMultDiv2(FL2FXCONST_DBL(0.707f), (FIXP_PCM)pSamples[drcComp->channelIdx[RS]])>>(DOWNMIX_SHIFT-1); /* Rs */
908 if (drcComp->channelIdx[RS] >= 0) tmp += fMultDiv2(FL2FXCONST_DBL(0.707f), (FIXP_PCM)pSamples[drcComp->channelIdx[RS]])>>(DOWNMIX_SHIFT-1); /* Rs */
910 if ((drcComp->channelIdx[RS] >
[all...]
/external/clang/lib/StaticAnalyzer/Checkers/
H A DCheckObjCDealloc.cpp127 void checkPreStmt(const ReturnStmt *RS, CheckerContext &C) const;
405 const ReturnStmt *RS, CheckerContext &C) const {
404 checkPreStmt( const ReturnStmt *RS, CheckerContext &C) const argument
H A DMallocChecker.cpp94 static RefState getAllocatedOfSizeZero(const RefState *RS) { argument
95 return RefState(AllocatedOfSizeZero, RS->getStmt(),
96 RS->getAllocationFamily());
104 static RefState getEscaped(const RefState *RS) { argument
105 return RefState(Escaped, RS->getStmt(), RS->getAllocationFamily());
373 const Expr *DeallocExpr, const RefState *RS,
905 const RefState *RS = State->get<RegionState>(Sym); local
906 if (RS) {
907 if (RS
1506 const RefState *RS = C.getState()->get<RegionState>(Sym); local
1670 ReportMismatchedDealloc(CheckerContext &C, SourceRange Range, const Expr *DeallocExpr, const RefState *RS, SymbolRef Sym, bool OwnershipTransferred) const argument
2065 const RefState *RS = C.getState()->get<RegionState>(Sym); local
2133 RegionStateTy RS = state->get<RegionState>(); local
2294 const RefState *RS = C.getState()->get<RegionState>(Sym); local
2346 RegionStateTy RS = state->get<RegionState>(); local
2544 retTrue(const RefState *RS) argument
2548 checkIfNewOrNewArrayFamily(const RefState *RS) argument
2625 const RefState *RS = state->get<RegionState>(Sym); local
2708 RegionStateTy RS = State->get<RegionState>(); local
[all...]
/external/llvm/include/llvm/CodeGen/
H A DRegAllocPBQP.h195 : RS(Unprocessed), NumOpts(0), DeniedOpts(0), OptUnsafeEdges(nullptr),
205 : RS(Other.RS), NumOpts(Other.NumOpts), DeniedOpts(Other.DeniedOpts),
221 : RS(Other.RS), NumOpts(Other.NumOpts), DeniedOpts(Other.DeniedOpts),
232 RS = Other.RS;
249 RS = Other.RS;
274 ReductionState getReductionState() const { return RS; }
275 setReductionState(ReductionState RS) argument
317 ReductionState RS; member in class:llvm::PBQP::RegAlloc::NodeMetadata
[all...]
/external/llvm/lib/CodeGen/
H A DPrologEpilogInserter.cpp51 static void doSpillCalleeSavedRegs(MachineFunction &MF, RegScavenger *RS,
57 static void doScavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger *RS);
93 std::function<void(MachineFunction &MF, RegScavenger *RS,
98 std::function<void(MachineFunction &MF, RegScavenger *RS)>
103 RegScavenger *RS; member in class:__anon12724::PEI
177 RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : nullptr;
190 SpillCalleeSavedRegisters(Fn, RS, MinCSFrameIndex, MaxCSFrameIndex,
195 TFI->processFunctionBeforeFrameFinalized(Fn, RS);
217 ScavengeFrameVirtualRegs(Fn, RS);
231 delete RS;
530 doSpillCalleeSavedRegs(MachineFunction &Fn, RegScavenger *RS, unsigned &MinCSFrameIndex, unsigned &MaxCSFrameIndex, const MBBVector &SaveBlocks, const MBBVector &RestoreBlocks) argument
1157 doScavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger *RS) argument
[all...]
H A DRegAllocPBQP.cpp799 std::ostringstream RS; local
800 RS << Round;
801 std::string GraphFileName = FullyQualifiedName + "." + RS.str() +
H A DMachineVerifier.cpp138 bool addPassed(const RegSet &RS) { argument
140 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
157 bool addRequired(const RegSet &RS) { argument
159 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
/external/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp728 unsigned RS = getRegState(Op1); local
731 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());
733 .addReg(Op1.getReg(), RS, Op1.getSubReg())
762 unsigned RS = getRegState(Op1); local
771 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
773 .addReg(Op1.getReg(), RS, HiSR);
796 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
799 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
802 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
808 .addReg(Op1.getReg(), RS
[all...]
H A DHexagonExpandCondsets.cpp582 RegisterRef RS = SO; local
583 if (TargetRegisterInfo::isVirtualRegister(RS.Reg)) {
584 const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg);
588 assert(TargetRegisterInfo::isPhysicalRegister(RS.Reg));
589 PhysR = RS.Reg;
591 unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
1232 RegisterRef RS = S1; local
1233 MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, true);
1238 RegisterRef RS local
[all...]
/external/llvm/utils/FileCheck/
H A DFileCheck.cpp164 bool AddRegExToRegEx(StringRef RS, unsigned &CurParen, SourceMgr &SM);
362 bool Pattern::AddRegExToRegEx(StringRef RS, unsigned &CurParen, argument
364 Regex R(RS);
367 SM.PrintMessage(SMLoc::getFromPointer(RS.data()), SourceMgr::DK_Error,
372 RegExStr += RS.str();
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DMachineVerifier.cpp129 bool addPassed(const RegSet &RS) { argument
131 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
148 bool addRequired(const RegSet &RS) { argument
150 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
/external/clang/lib/Sema/
H A DSemaLambda.cpp686 const ReturnStmt *RS = *I; local
687 const Expr *RetE = RS->getRetValue();
697 Diag(RS->getLocStart(),
/external/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp727 MachineBasicBlock &MBB, MachineInstr &MI, RegScavenger *RS, unsigned TmpReg,
763 RS->enterBasicBlock(Entry);
765 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
766 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
726 calculateLDSSpillAddress( MachineBasicBlock &MBB, MachineInstr &MI, RegScavenger *RS, unsigned TmpReg, unsigned FrameOffset, unsigned Size) const argument
/external/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp579 RegScavenger RS; local
597 RS.enterBasicBlock(*MBB);
609 RS.forward(MBBI);
616 if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12))
625 BitVector BV = RS.getRegsAvailable(Subtarget.isPPC64() ? &PPC::G8RCRegClass :
1379 RegScavenger *RS) const {
1380 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1442 RegScavenger *RS) const {
1445 addScavengingSpillSlot(MF, RS);
[all...]
/external/llvm/lib/Transforms/IPO/
H A DMergeFunctions.cpp723 const ConstantStruct *RS = cast<ConstantStruct>(R); local
730 cast<Constant>(RS->getOperand(i))))
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp66 RegScavenger *RS; member in struct:__anon19999::ARMLoadStoreOpt
1017 RS->forward(prior(Loc));
1190 RS->enterBasicBlock(&MBB);
1284 unsigned Scratch = RS->FindUnusedReg(ARM::GPRRegisterClass);
1286 RS->forward(prior(MBBI));
1307 // RS may be pointing to an instruction that's deleted.
1308 RS->skipTo(prior(MBBI));
1314 RS->forward(prior(MBBI));
1383 RS = new RegScavenger();
1395 delete RS;
[all...]
/external/valgrind/VEX/priv/
H A Dguest_s390_toIR.c14389 } RS; member in union:__anon23646
15312 case 0x86: s390_format_RS_RRRD(s390_irgen_BXH, ovl.fmt.RS.r1, ovl.fmt.RS.r3,
15313 ovl.fmt.RS.b2, ovl.fmt.RS.d2); goto ok;
15314 case 0x87: s390_format_RS_RRRD(s390_irgen_BXLE, ovl.fmt.RS.r1, ovl.fmt.RS.r3,
15315 ovl.fmt.RS.b2, ovl.fmt.RS.d2); goto ok;
15316 case 0x88: s390_format_RS_R0RD(s390_irgen_SRL, ovl.fmt.RS
[all...]
/external/robolectric/v1/lib/main/
H A Dsqlite-jdbc-3.7.2.jarMETA-INF/ META-INF/MANIFEST.MF META-INF/maven/ META-INF/maven/org. ...
H A Dh2-1.2.147.jarMETA-INF/MANIFEST.MF META-INF/services/java.sql.Driver org/h2/api/AggregateFunction ...
/external/zxing/core/
H A Dcore.jarMETA-INF/ META-INF/MANIFEST.MF com/ com/google/ com/google/zxing/ com/google/zxing/oned/ ...
/external/dagger2/lib/
H A Dauto-value-1.4.1.jarMETA-INF/ META-INF/MANIFEST.MF com/ com/google/ com/google/auto/ com/google/auto/value/ ...
/external/owasp/sanitizer/distrib/lib/
H A Dguava.jarMETA-INF/ META-INF/MANIFEST.MF com/ com/google/ com/google/common/ com/google/common/collect/ ...
/external/owasp/sanitizer/lib/guava-libraries/
H A Dguava.jarMETA-INF/ META-INF/MANIFEST.MF com/ com/google/ com/google/common/ com/google/common/collect/ ...

Completed in 1359 milliseconds

123