Searched defs:STI (Results 76 - 100 of 222) sorted by relevance

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/external/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp29 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, argument
31 : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {}
41 const MCSubtargetInfo &STI,
43 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false);
47 const MCSubtargetInfo &STI,
49 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true);
414 if (STI.getFeatureBits()[PPC::FeatureQPX]) {
416 decodeInstruction(DecoderTableQPX32, MI, Inst, Address, this, STI);
421 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
40 createPPCDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument
46 createPPCLEDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) argument
/external/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcMCTargetDesc.cpp110 createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { argument
/external/llvm/lib/Target/SystemZ/InstPrinter/
H A DSystemZInstPrinter.cpp54 const MCSubtargetInfo &STI) {
52 printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) argument
/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInfo.cpp31 WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI) argument
34 RI(STI.getTargetTriple()) {}
/external/llvm/lib/Target/X86/InstPrinter/
H A DX86ATTInstPrinter.cpp41 StringRef Annot, const MCSubtargetInfo &STI) {
60 (STI.getFeatureBits()[X86::Mode64Bit])) {
40 printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, const MCSubtargetInfo &STI) argument
H A DX86IntelInstPrinter.cpp37 const MCSubtargetInfo &STI) {
35 printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, const MCSubtargetInfo &STI) argument
/external/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp38 X86FrameLowering::X86FrameLowering(const X86Subtarget &STI, argument
41 STI.is64Bit() ? -8 : -4),
42 STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
45 Is64Bit = STI.is64Bit();
46 IsLP64 = STI.isTarget64BitLP64();
48 Uses64BitFramePtr = STI.isTarget64BitLP64() || STI
[all...]
H A DX86WinAllocaExpander.cpp59 const X86Subtarget *STI; member in class:__anon13372::X86WinAllocaExpander
212 bool Is64Bit = STI->is64Bit();
247 STI->getFrameLowering()->emitStackProbe(*MBB->getParent(), *MBB, MI, DL,
274 STI = &MF.getSubtarget<X86Subtarget>();
275 TII = STI->getInstrInfo();
276 TRI = STI->getRegisterInfo();
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DLLVMTargetMachine.cpp141 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); local
148 getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI, STI);
154 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); local
155 MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI, *Context);
172 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI,
249 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); local
250 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(),STI, *Ctx);
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DThumb2InstrInfo.cpp34 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI) argument
35 : ARMBaseInstrInfo(STI), RI(*this, STI) {
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/
H A DMBlazeMCCodeEmitter.cpp101 const MCSubtargetInfo &STI,
103 return new MBlazeMCCodeEmitter(MCII, STI, Ctx);
100 createMBlazeMCCodeEmitter(const MCInstrInfo &MCII, const MCSubtargetInfo &STI, MCContext &Ctx) argument
/external/swiftshader/third_party/LLVM/lib/Target/PTX/InstPrinter/
H A DPTXInstPrinter.cpp30 const MCSubtargetInfo &STI) :
33 setAvailableFeatures(STI.getFeatureBits());
29 PTXInstPrinter(const MCAsmInfo &MAI, const MCSubtargetInfo &STI) argument
/external/swiftshader/third_party/LLVM/lib/Target/PTX/
H A DPTXTargetMachine.cpp143 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); local
150 getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI, STI);
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.cpp109 const MCSubtargetInfo &STI) {
106 createPPCMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCSubtargetInfo &STI) argument
/external/llvm/include/llvm/Target/
H A DTargetMachine.h100 const MCSubtargetInfo *STI; member in class:llvm::TargetMachine
159 const MCSubtargetInfo *getMCSubtargetInfo() const { return STI; }
/external/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp46 const TargetSubtargetInfo &STI = IS->MF->getSubtarget(); local
47 TRI = STI.getRegisterInfo();
49 TII = STI.getInstrInfo();
50 ResourcesModel.reset(TII->CreateTargetScheduleState(STI));
/external/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp59 const MCSubtargetInfo *STI = local
61 if (!STI)
70 MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI, *Ctx);
92 TheTarget, MAI, MRI, STI, MII, Ctx, DisAsm, IP);
163 const MCSubtargetInfo *STI = DC->getSubtargetInfo(); local
164 InstrItineraryData IID = STI->getInstrItineraryForCPU(DC->getCPU());
182 const MCSubtargetInfo *STI = DC->getSubtargetInfo(); local
183 const MCSchedModel SCModel = STI->getSchedModel();
206 const MCWriteLatencyEntry *WLEntry = STI->getWriteLatencyEntry(SCDesc,
/external/llvm/lib/MC/
H A DWinCOFFStreamer.cpp45 const MCSubtargetInfo &STI) {
51 getAssembler().getEmitter().encodeInstruction(Inst, VecOS, Fixups, STI);
44 EmitInstToData(const MCInst &Inst, const MCSubtargetInfo &STI) argument
/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp72 StringRef Annot, const MCSubtargetInfo &STI) {
86 printSBitModifierOperand(MI, 6, STI, O);
87 printPredicateOperand(MI, 4, STI, O);
108 printSBitModifierOperand(MI, 5, STI, O);
109 printPredicateOperand(MI, 3, STI, O);
133 printPredicateOperand(MI, 2, STI, O);
137 printRegisterList(MI, 4, STI, O);
147 printPredicateOperand(MI, 4, STI, O);
162 printPredicateOperand(MI, 2, STI, O);
166 printRegisterList(MI, 4, STI,
71 printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) argument
272 printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) argument
312 printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) argument
[all...]
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp34 static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, argument
36 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
66 static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, argument
68 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
78 static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, argument
80 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
95 static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, argument
97 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
/external/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp275 const ARMSubtarget &STI = local
277 if (!STI.isThumb2())
280 TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
281 TRI = STI.getRegisterInfo();
282 restrictIT = STI.restrictIT();
H A DThumb2InstrInfo.cpp32 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI) argument
33 : ARMBaseInstrInfo(STI), RI() {}
/external/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.h56 VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM) argument
58 ResourcesModel = STI.getInstrInfo()->CreateTargetScheduleState(STI);
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonInstPrinter.cpp54 StringRef Annot, const MCSubtargetInfo &STI) {
53 printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, const MCSubtargetInfo &STI) argument
H A DHexagonMCChecker.cpp226 HexagonMCChecker::HexagonMCChecker(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &mcb, MCInst &mcbdx, argument
228 : MCB(mcb), MCBDX(mcbdx), RI(ri), MCII(MCII), STI(STI),
507 HexagonMCShuffler MCS(MCII, STI, MCB);
516 HexagonMCShuffler MCSDX(MCII, STI, MCBDX);

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