/external/llvm/lib/CodeGen/ |
H A D | AllocationOrder.cpp | 30 AllocationOrder::AllocationOrder(unsigned VirtReg, argument 37 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); 38 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix);
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H A D | LiveIntervalUnion.cpp | 29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { argument 40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); 50 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg); 52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); 56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { argument 67 assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval"); 104 bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const { 106 std::find(InterferingVRegs.begin(), InterferingVRegs.end(), VirtReg); 130 if (VirtReg->empty() || LiveUnion->empty()) { 135 // In most cases, the union will start before VirtReg [all...] |
H A D | LiveRegMatrix.cpp | 97 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { argument 98 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) 100 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); 101 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); 103 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, 106 Matrix[Unit].unify(VirtReg, Range); 114 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { argument 115 unsigned PhysReg = VRM->getPhys(VirtReg.reg); 116 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg 139 checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 157 checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 171 query(LiveInterval &VirtReg, unsigned RegUnit) argument 179 checkInterference(LiveInterval &VirtReg, unsigned PhysReg) argument [all...] |
H A D | RegAllocBasic.cpp | 102 unsigned selectOrSplit(LiveInterval &VirtReg, 111 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, 164 // that interfere with VirtReg. The newly spilled or split live intervals are 166 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, argument 174 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); 180 if (!Intf->isSpillable() || Intf->weight > VirtReg.weight) 186 " interferences with " << VirtReg << "\n"); 220 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, argument 226 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix); 229 switch (Matrix->checkInterference(VirtReg, PhysRe [all...] |
H A D | RegisterCoalescer.h | 66 CoalescerPair(unsigned VirtReg, unsigned PhysReg, argument 68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
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H A D | VirtRegMap.cpp | 82 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) { argument 83 unsigned Hint = MRI->getSimpleHint(VirtReg); 88 return getPhys(VirtReg) == Hint; 91 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) { argument 92 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg); 291 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx); local 292 if (MRI->reg_nodbg_empty(VirtReg)) 294 LiveInterval &LI = LIS->getInterval(VirtReg); 299 unsigned PhysReg = VRM->getPhys(VirtReg); 398 unsigned VirtReg local [all...] |
H A D | PHIElimination.cpp | 200 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs. 202 static bool isImplicitlyDefined(unsigned VirtReg, argument 204 for (MachineInstr &DI : MRI->def_instructions(VirtReg))
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H A D | RegAllocFast.cpp | 71 unsigned VirtReg; // Virtual register number. member in struct:__anon12728::RAFast::LiveReg 77 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){} 80 return TargetRegisterInfo::virtReg2Index(VirtReg); 171 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC); 176 void killVirtReg(unsigned VirtReg); 178 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg); 184 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { argument 185 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); 187 LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const { 188 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); 205 getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) argument 260 killVirtReg(unsigned VirtReg) argument 270 spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) argument 516 assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) argument 527 const unsigned VirtReg = LRI->VirtReg; local 598 defineVirtReg(MachineInstr &MI, unsigned OpNum, unsigned VirtReg, unsigned Hint) argument 632 reloadVirtReg(MachineInstr &MI, unsigned OpNum, unsigned VirtReg, unsigned Hint) argument [all...] |
H A D | LiveDebugVariables.cpp | 310 /// lookupVirtReg - Find the EC leader for VirtReg or null. 311 UserValue *lookupVirtReg(unsigned VirtReg); 349 void mapVirtReg(unsigned VirtReg, UserValue *EC); 479 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) { argument 480 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Only map VirtRegs"); 481 UserValue *&Leader = virtRegToEqClass[VirtReg]; 485 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) { argument 486 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg)) 923 unsigned VirtReg = Loc.getReg(); local 924 if (VRM.isAssignedReg(VirtReg) [all...] |
H A D | MachineBasicBlock.cpp | 381 unsigned VirtReg = I->getOperand(0).getReg(); local 382 if (!MRI.constrainRegClass(VirtReg, RC)) 384 return VirtReg; 388 unsigned VirtReg = MRI.createVirtualRegister(RC); local 389 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg) 393 return VirtReg;
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | AllocationOrder.cpp | 25 AllocationOrder::AllocationOrder(unsigned VirtReg, argument 29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg); 31 VRM.getRegInfo().getRegAllocationHint(VirtReg);
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H A D | LiveIntervalUnion.cpp | 28 void LiveIntervalUnion::unify(LiveInterval &VirtReg) { argument 29 if (VirtReg.empty()) 34 LiveInterval::iterator RegPos = VirtReg.begin(); 35 LiveInterval::iterator RegEnd = VirtReg.end(); 39 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); 49 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg); 51 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); 55 void LiveIntervalUnion::extract(LiveInterval &VirtReg) { argument 56 if (VirtReg.empty()) 61 LiveInterval::iterator RegPos = VirtReg [all...] |
H A D | LiveIntervalUnion.h | 92 void unify(LiveInterval &VirtReg); 95 void extract(LiveInterval &VirtReg); 112 LiveInterval *VirtReg; member in class:llvm::LiveIntervalUnion::Query 113 LiveInterval::iterator VirtRegI; // current position in VirtReg 122 Query(): LiveUnion(), VirtReg(), Tag(0), UserTag(0) {} 125 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false), 131 VirtReg = NULL; 142 if (UserTag == UTag && VirtReg == VReg && 149 VirtReg = VReg; 155 assert(VirtReg [all...] |
H A D | VirtRegMap.cpp | 183 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, argument 194 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo))); 197 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) { argument 199 MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo))); 281 unsigned VirtReg = MO.getReg(); local 282 unsigned PhysReg = getPhys(VirtReg); 283 assert(PhysReg != NO_PHYS_REG && "Instruction uses unmapped VirtReg");
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H A D | PrologEpilogInserter.cpp | 822 unsigned VirtReg = 0; local 842 if (Reg != VirtReg) { 848 VirtReg = Reg;
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H A D | RegAllocBasic.cpp | 125 virtual unsigned selectOrSplit(LiveInterval &VirtReg, 268 LiveInterval &VirtReg = *I->second; local 270 PhysReg2LiveUnion[RegNum].unify(VirtReg); 272 enqueue(&VirtReg); 276 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) { argument 277 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) 279 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); 280 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); 282 PhysReg2LiveUnion[PhysReg].unify(VirtReg); 286 unassign(LiveInterval &VirtReg, unsigned PhysReg) argument 367 checkPhysRegInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 377 spillReg(LiveInterval& VirtReg, unsigned PhysReg, SmallVectorImpl<LiveInterval*> &SplitVRegs) argument 406 spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, SmallVectorImpl<LiveInterval*> &SplitVRegs) argument 482 selectOrSplit(LiveInterval &VirtReg, SmallVectorImpl<LiveInterval*> &SplitVRegs) argument [all...] |
H A D | RegAllocFast.cpp | 150 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC); 155 void killVirtReg(unsigned VirtReg); 157 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg); 165 unsigned VirtReg, unsigned Hint); 167 unsigned VirtReg, unsigned Hint); 176 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { argument 178 int SS = StackSlotForVirtReg[VirtReg]; 187 StackSlotForVirtReg[VirtReg] = FrameIdx; 235 void RAFast::killVirtReg(unsigned VirtReg) { argument 236 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) 245 spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) argument 480 const unsigned VirtReg = LRE.first; local 541 defineVirtReg(MachineInstr *MI, unsigned OpNum, unsigned VirtReg, unsigned Hint) argument 575 reloadVirtReg(MachineInstr *MI, unsigned OpNum, unsigned VirtReg, unsigned Hint) argument [all...] |
H A D | RegAllocGreedy.cpp | 138 LiveRangeStage getStage(const LiveInterval &VirtReg) const { 139 return ExtraRegInfo[VirtReg.reg].Stage; 142 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { argument 144 ExtraRegInfo[VirtReg.reg].Stage = Stage; 358 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { argument 359 if (unsigned PhysReg = VRM->getPhys(VirtReg)) { 360 unassign(LIS->getInterval(VirtReg), PhysReg); 368 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { argument 369 unsigned PhysReg = VRM->getPhys(VirtReg); 374 LiveInterval &LI = LIS->getInterval(VirtReg); 444 tryAssign(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<LiveInterval*> &NewVRegs) argument 521 canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, bool IsHint, EvictionCost &MaxCost) argument 582 evictInterference(LiveInterval &VirtReg, unsigned PhysReg, SmallVectorImpl<LiveInterval*> &NewVRegs) argument 613 tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<LiveInterval*> &NewVRegs, unsigned CostPerUseLimit) argument [all...] |
H A D | VirtRegMap.h | 211 /// @brief returns true if VirtReg is assigned to its preferred physreg. 212 bool hasPreferredPhys(unsigned VirtReg) { argument 213 return getPhys(VirtReg) == getRegAllocPref(VirtReg); 226 /// getOriginal - Return the original virtual register that VirtReg descends 230 unsigned getOriginal(unsigned VirtReg) const { 231 unsigned Orig = getPreSplitReg(VirtReg); 232 return Orig ? Orig : VirtReg; 449 void setIsImplicitlyDefined(unsigned VirtReg) { argument 450 ImplicitDefed.set(TargetRegisterInfo::virtReg2Index(VirtReg)); [all...] |
H A D | VirtRegRewriter.cpp | 368 // VirtReg - The virtual register itself. 369 unsigned VirtReg; member in struct:__anon19901::ReusedOp 374 AssignedPhysReg(apr), VirtReg(vreg) {} 396 unsigned VirtReg) { 403 AssignedPhysReg, VirtReg)); 437 unsigned GetRegForReload(unsigned VirtReg, unsigned PhysReg, MachineInstr *MI, argument 445 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg); 692 unsigned VirtReg = MO.getReg(); 693 if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) 696 unsigned Phys = VRM.getPhys(VirtReg); 394 addReuse(unsigned OpNo, unsigned StackSlotOrReMat, unsigned PhysRegReused, unsigned AssignedPhysReg, unsigned VirtReg) argument [all...] |
H A D | InlineSpiller.cpp | 834 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, argument 837 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); 843 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) 859 markValueUsed(&VirtReg, ParentVNI); 864 // If the instruction also writes VirtReg.reg, it had better not require the 868 tie(Reads, Writes) = MI->readsWritesVirtualRegister(VirtReg.reg, &Ops); 873 markValueUsed(&VirtReg, ParentVNI); 902 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
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H A D | LiveDebugVariables.cpp | 303 /// lookupVirtReg - Find the EC leader for VirtReg or null. 304 UserValue *lookupVirtReg(unsigned VirtReg); 335 void mapVirtReg(unsigned VirtReg, UserValue *EC); 429 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) { argument 430 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Only map VirtRegs"); 431 UserValue *&Leader = virtRegToEqClass[VirtReg]; 435 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) { argument 436 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg)) 885 unsigned VirtReg = Loc.getReg(); local 886 if (VRM.isAssignedReg(VirtReg) [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | LiveIntervalUnion.h | 87 void unify(LiveInterval &VirtReg, const LiveRange &Range); 88 void unify(LiveInterval &VirtReg) { argument 89 unify(VirtReg, VirtReg); 93 void extract(LiveInterval &VirtReg, const LiveRange &Range); 94 void extract(LiveInterval &VirtReg) { argument 95 extract(VirtReg, VirtReg); 113 LiveInterval *VirtReg; member in class:llvm::LiveIntervalUnion::Query 114 LiveInterval::iterator VirtRegI; // current position in VirtReg [all...] |
H A D | ScheduleDAGInstrs.h | 36 unsigned VirtReg; member in struct:llvm::VReg2SUnit 41 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {} 44 return TargetRegisterInfo::virtReg2Index(VirtReg);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.cpp | 255 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, argument 262 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 273 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
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