Searched defs:base_level (Results 1 - 20 of 20) sorted by relevance

/external/mesa3d/src/gallium/auxiliary/util/
H A Du_gen_mipmap.c53 * \param base_level the first mipmap level to use as a src
60 enum pipe_format format, uint base_level, uint last_level,
92 assert(last_level > base_level);
103 for (dstLevel = base_level + 1; dstLevel <= last_level; dstLevel++) {
59 util_gen_mipmap(struct pipe_context *pipe, struct pipe_resource *pt, enum pipe_format format, uint base_level, uint last_level, uint first_layer, uint last_layer, uint filter) argument
H A Du_blitter.c1873 unsigned base_level, unsigned last_level,
1925 for (src_level = base_level; src_level < last_level; src_level++) {
1870 util_blitter_generate_mipmap(struct blitter_context *blitter, struct pipe_resource *tex, enum pipe_format format, unsigned base_level, unsigned last_level, unsigned first_layer, unsigned last_layer) argument
/external/mesa3d/src/gallium/state_trackers/nine/
H A Dbasetexture9.c386 unsigned base_level = 0; local
406 last_layer = util_max_layer(This->view[0]->texture, base_level);
410 base_level, last_level,
/external/mesa3d/src/gallium/drivers/r300/
H A Dr300_state_derived.c795 unsigned base_level, min_level, level_count, i, j, size; local
828 base_level = view->base.u.tex.first_level;
831 tex->b.b.last_level - base_level,
832 view->base.u.tex.last_level - base_level);
834 if (base_level + min_level) {
842 base_level += min_level;
844 offset = tex->tex.offset_in_bytes[base_level];
848 base_level,
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_sampler_state.c91 unsigned base_level,
149 ss[0] |= SET_FIELD(base_level, BRW_SAMPLER_BASE_MIPLEVEL);
522 const unsigned base_level = local
553 base_level, min_lod, max_lod, lod_bias,
80 brw_emit_sampler_state(struct brw_context *brw, uint32_t *ss, uint32_t batch_offset_for_sampler_state, unsigned min_filter, unsigned mag_filter, unsigned mip_filter, unsigned max_anisotropy, unsigned address_rounding, unsigned wrap_s, unsigned wrap_t, unsigned wrap_r, unsigned base_level, unsigned min_lod, unsigned max_lod, int lod_bias, unsigned shadow_function, bool non_normalized_coordinates, uint32_t border_color_offset) argument
/external/mesa3d/src/gallium/drivers/noop/
H A Dnoop_pipe.c298 unsigned base_level,
295 noop_generate_mipmap(struct pipe_context *ctx, struct pipe_resource *resource, enum pipe_format format, unsigned base_level, unsigned last_level, unsigned first_layer, unsigned last_layer) argument
/external/mesa3d/src/gallium/drivers/svga/
H A Dsvga_resource_texture.c1245 unsigned base_level,
1277 templ.u.tex.first_level = base_level;
1242 svga_texture_generate_mipmap(struct pipe_context *pipe, struct pipe_resource *pt, enum pipe_format format, unsigned base_level, unsigned last_level, unsigned first_layer, unsigned last_layer) argument
/external/mesa3d/src/amd/vulkan/
H A Dradv_image.c194 unsigned base_level, unsigned first_level,
211 state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level,
191 si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *image, const struct radeon_surf_level *base_level_info, unsigned base_level, unsigned first_level, unsigned block_width, bool is_stencil, uint32_t *state) argument
/external/mesa3d/src/gallium/drivers/ddebug/
H A Ddd_draw.c1220 unsigned base_level,
1233 call.info.generate_mipmap.base_level = base_level;
1239 result = pipe->generate_mipmap(pipe, res, format, base_level, last_level,
1217 dd_context_generate_mipmap(struct pipe_context *_pipe, struct pipe_resource *res, enum pipe_format format, unsigned base_level, unsigned last_level, unsigned first_layer, unsigned last_layer) argument
H A Ddd_pipe.h100 unsigned base_level; member in struct:call_generate_mipmap
/external/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_blit.c1163 unsigned base_level, unsigned last_level,
1174 vi_dcc_disable_if_incompatible_format(&sctx->b, tex, base_level,
1177 base_level, first_layer, last_layer);
1180 assert(base_level < last_level);
1181 rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1182 last_level - base_level);
1186 base_level, last_level,
1160 si_generate_mipmap(struct pipe_context *ctx, struct pipe_resource *tex, enum pipe_format format, unsigned base_level, unsigned last_level, unsigned first_layer, unsigned last_layer) argument
H A Dsi_descriptors.c371 * \param base_level the level of BASE_ADDRESS
379 unsigned base_level, unsigned first_level,
400 state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level,
448 rview->base_level,
377 si_set_mutable_tex_desc_fields(struct r600_texture *tex, const struct radeon_surf_level *base_level_info, unsigned base_level, unsigned first_level, unsigned block_width, bool is_stencil, uint32_t *state) argument
H A Dsi_pipe.h131 unsigned base_level; member in struct:si_sampler_view
H A Dsi_state.c3035 unsigned base_level, first_level, last_level; local
3076 base_level = 0;
3086 base_level = force_level;
3162 view->base_level_info = &surflevel[base_level];
3163 view->base_level = base_level;
/external/mesa3d/src/gallium/drivers/svga/include/
H A Dsvga3d_surfacedefs.h952 svga3dsurface_get_mip_size(SVGA3dSize base_level, uint32 mip_level) argument
956 size.width = max_t(uint32, base_level.width >> mip_level, 1);
957 size.height = max_t(uint32, base_level.height >> mip_level, 1);
958 size.depth = max_t(uint32, base_level.depth >> mip_level, 1);
/external/webp/src/dec/
H A Dframe_dec.c272 int base_level; local
274 base_level = dec->segment_hdr_.filter_strength_[s];
276 base_level += hdr->level_;
279 base_level = hdr->level_;
283 int level = base_level;
/external/mesa3d/src/gallium/drivers/trace/
H A Dtr_context.c1407 unsigned base_level,
1424 trace_dump_arg(uint, base_level);
1429 ret = pipe->generate_mipmap(pipe, res, format, base_level, last_level,
1404 trace_context_generate_mipmap(struct pipe_context *_pipe, struct pipe_resource *res, enum pipe_format format, unsigned base_level, unsigned last_level, unsigned first_layer, unsigned last_layer) argument
/external/selinux/libsepol/src/
H A Dlink.c671 level_datum_t *level, *base_level; local
677 base_level = hashtab_search(state->base->p_levels.table, id);
678 if (!base_level) {
704 base_level->level->sens;
/external/mesa3d/src/gallium/drivers/r600/
H A Devergreen_state.c673 unsigned base_level, first_level, last_level; local
738 base_level = 0;
746 base_level = force_level;
754 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
757 switch (surflevel[base_level].mode) {
818 view->tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
833 view->tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
/external/mesa3d/src/intel/isl/
H A Disl.h921 uint32_t base_level; member in struct:isl_view

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