Searched defs:getReg (Results 1 - 25 of 35) sorted by relevance

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/external/llvm/include/llvm/MC/
H A DMachineLocation.h54 unsigned getReg() const { return Register; } function
H A DMCInst.h63 unsigned getReg() const { function in class:llvm::MCOperand
/external/swiftshader/third_party/LLVM/include/llvm/MC/
H A DMachineLocation.h52 unsigned getReg() const { return Register; } function in class:llvm::MachineLocation
H A DMCInst.h57 /// getReg - Returns the register number.
58 unsigned getReg() const { function in class:llvm::MCOperand
/external/llvm/include/llvm/CodeGen/
H A DLiveRangeEdit.h143 unsigned getReg() const { return getParent().reg; } function in class:llvm::LiveRangeEdit
176 return createEmptyIntervalFrom(getReg());
180 return createFrom(getReg());
H A DCallingConvLower.h77 static CCValAssign getReg(unsigned ValNo, MVT ValVT, function in class:llvm::CCValAssign
95 Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP);
127 return getReg(ValNo, ValVT, ExtraInfo, LocVT, HTP);
H A DMachineOperand.h266 /// getReg - Returns the register number.
267 unsigned getReg() const { function in class:llvm::MachineOperand
H A DMachineFrameInfo.h46 unsigned getReg() const { return Reg; } function in class:llvm::CalleeSavedInfo
H A DScheduleDAG.h215 /// getReg - Return the register associated with this edge. This is
218 unsigned getReg() const { function in class:llvm::SDep
220 "getReg called on non-register dependence edge!");
/external/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp91 unsigned getReg(ValueType Entry);
111 !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
134 unsigned SrcReg = I->getOperand(0).getReg();
147 MVT::SimpleValueType Ty = getRegTy(MI.getOperand(0).getReg(), MF);
152 if (MO.isReg() && MO.getReg() == Reg) {
229 getCallTargetRegOpnd(*I)->setReg(getReg(Entry));
258 Reg = MO->getReg();
287 unsigned OptimizePICCall::getReg(ValueType Entry) { function in class:OptimizePICCall
H A DMipsFastISel.cpp68 unsigned getReg() const { function in class:__anon13197::final::Address
501 return Addr.getReg() != 0;
548 return Addr.getReg() != 0;
758 emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
809 emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
1860 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DLiveRangeEdit.h107 unsigned getReg() const { return parent_.reg; } function in class:llvm::LiveRangeEdit
134 return createFrom(getReg(), LIS, VRM);
/external/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp70 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { function
206 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
218 unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
H A DCallingConvLower.h67 static CCValAssign getReg(unsigned ValNo, MVT ValVT, function in class:llvm::CCValAssign
85 Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP);
H A DMachineFrameInfo.h43 unsigned getReg() const { return Reg; } function in class:llvm::CalleeSavedInfo
H A DMachineOperand.h220 /// getReg - Returns the register number.
221 unsigned getReg() const { function in class:llvm::MachineOperand
H A DScheduleDAG.h199 /// getReg - Return the register associated with this edge. This is
202 unsigned getReg() const { function in class:llvm::SDep
204 "getReg called on non-register dependence edge!");
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/AsmParser/
H A DMBlazeAsmParser.cpp141 unsigned getReg() const { function in struct:__anon20056::MBlazeOperand
189 Inst.addOperand(MCOperand::CreateReg(getReg()));
286 OS << getMBlazeRegisterNumbering(getReg()) << ">";
377 Op = MBlazeOperand::CreateMem(Base.getReg(), Offset.getReg(), S, E);
379 Op = MBlazeOperand::CreateMem(Base.getReg(), Offset.getImm(), S, E);
/external/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp536 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { function
617 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
620 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
643 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
645 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
649 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
687 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
690 MI.addOperand(MCOperand::createReg(getReg(Decode
[all...]
/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp74 unsigned getReg() const { function in class:__anon13306::final::Address
249 if (S == 1 && Addr.isRegBase() && Addr.getReg() == 0) {
321 return Addr.getReg() != 0;
326 unsigned Reg = Addr.getReg();
350 MIB.addReg(Addr.getReg());
/external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp161 unsigned getReg() const { function in struct:__anon20123::X86Operand
297 Inst.addOperand(MCOperand::CreateReg(getReg()));
817 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
830 if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) {
859 unsigned reg = Op2->getReg();
889 unsigned reg = Op1->getReg();
/external/swiftshader/third_party/LLVM/utils/TableGen/
H A DCodeGenRegisters.cpp63 CodeGenRegister *SR = RegBank.getReg(SubList[i]);
75 CodeGenRegister *SR = RegBank.getReg(SubList[i]);
284 Members.insert(RegBank.getReg((*Elements)[i]));
294 CodeGenRegister *Reg = RegBank.getReg(Order.back());
371 if (contains(RegBank.getReg(Super.Orders[i][j])))
528 getReg(Regs[i]);
536 getReg((*TupRegs)[j]);
564 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) { function in class:CodeGenRegBank
714 CodeGenRegister *Reg2 = getReg(RegList[i2]);
807 const CodeGenRegister *Reg = getReg(
[all...]
/external/libunwind_llvm/src/
H A DUnwindCursor.hpp386 virtual unw_word_t getReg(int) { _LIBUNWIND_ABORT("getReg not implemented"); } function in class:libunwind::AbstractUnwindCursor
431 virtual unw_word_t getReg(int);
472 (pint_t)this->getReg(UNW_REG_IP),
632 unw_word_t UnwindCursor<A, R>::getReg(int regNum) { function in class:libunwind::UnwindCursor
1204 pint_t pc = (pint_t)this->getReg(UNW_REG_IP);
1353 setReg(UNW_REG_SP, getReg(UNW_REG_SP) + _info.gp);
1367 return _addressSpace.findFunctionName((pint_t)this->getReg(UNW_REG_IP),
/external/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp315 unsigned getReg() const { function in class:__anon13115::CountValue
418 unsigned PhiOpReg = Phi->getOperand(i).getReg();
426 unsigned IndReg = DI->getOperand(1).getReg();
430 unsigned UpdReg = DI->getOperand(0).getReg();
579 IVReg = IV_Phi->getOperand(i).getReg(); // Want IV reg after bump.
645 if (Op2.isImm() || Op1.getReg() == IVReg)
665 unsigned R = InitialValue->getReg();
672 unsigned R = EndValue->getReg();
699 const MachineInstr *StartValInstr = MRI->getVRegDef(Start->getReg());
705 const MachineInstr *EndValInstr = MRI->getVRegDef(End->getReg());
[all...]
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp127 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i]));
142 CodeGenRegister *Reg = RegBank.getReg(Aliases[i]);
174 const CodeGenRegister *getReg() const { assert(isValid()); return *RegI; } function in class:__anon13872::RegUnitIterator
683 const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]);
696 CodeGenRegister *Reg = RegBank.getReg(Order.back());
760 if (contains(RegBank.getReg(Super.Orders[i][j])))
943 getReg(Regs[i]);
953 getReg(RC);
1027 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) { function in class:CodeGenRegBank
1393 if (Reg != UnitI.getReg()) {
[all...]

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