1//===-- llvm/CallingConvLower.h - Calling Conventions -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the CCState and CCValAssign classes, used for lowering
11// and implementing calling conventions.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_CALLINGCONVLOWER_H
16#define LLVM_CODEGEN_CALLINGCONVLOWER_H
17
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/IR/CallingConv.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/Target/TargetCallingConv.h"
24
25namespace llvm {
26class CCState;
27class MVT;
28class TargetMachine;
29class TargetRegisterInfo;
30
31/// CCValAssign - Represent assignment of one arg/retval to a location.
32class CCValAssign {
33public:
34  enum LocInfo {
35    Full,      // The value fills the full location.
36    SExt,      // The value is sign extended in the location.
37    ZExt,      // The value is zero extended in the location.
38    AExt,      // The value is extended with undefined upper bits.
39    SExtUpper, // The value is in the upper bits of the location and should be
40               // sign extended when retrieved.
41    ZExtUpper, // The value is in the upper bits of the location and should be
42               // zero extended when retrieved.
43    AExtUpper, // The value is in the upper bits of the location and should be
44               // extended with undefined upper bits when retrieved.
45    BCvt,      // The value is bit-converted in the location.
46    VExt,      // The value is vector-widened in the location.
47               // FIXME: Not implemented yet. Code that uses AExt to mean
48               // vector-widen should be fixed to use VExt instead.
49    FPExt,     // The floating-point value is fp-extended in the location.
50    Indirect   // The location contains pointer to the value.
51    // TODO: a subset of the value is in the location.
52  };
53
54private:
55  /// ValNo - This is the value number begin assigned (e.g. an argument number).
56  unsigned ValNo;
57
58  /// Loc is either a stack offset or a register number.
59  unsigned Loc;
60
61  /// isMem - True if this is a memory loc, false if it is a register loc.
62  unsigned isMem : 1;
63
64  /// isCustom - True if this arg/retval requires special handling.
65  unsigned isCustom : 1;
66
67  /// Information about how the value is assigned.
68  LocInfo HTP : 6;
69
70  /// ValVT - The type of the value being assigned.
71  MVT ValVT;
72
73  /// LocVT - The type of the location being assigned to.
74  MVT LocVT;
75public:
76
77  static CCValAssign getReg(unsigned ValNo, MVT ValVT,
78                            unsigned RegNo, MVT LocVT,
79                            LocInfo HTP) {
80    CCValAssign Ret;
81    Ret.ValNo = ValNo;
82    Ret.Loc = RegNo;
83    Ret.isMem = false;
84    Ret.isCustom = false;
85    Ret.HTP = HTP;
86    Ret.ValVT = ValVT;
87    Ret.LocVT = LocVT;
88    return Ret;
89  }
90
91  static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT,
92                                  unsigned RegNo, MVT LocVT,
93                                  LocInfo HTP) {
94    CCValAssign Ret;
95    Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP);
96    Ret.isCustom = true;
97    return Ret;
98  }
99
100  static CCValAssign getMem(unsigned ValNo, MVT ValVT,
101                            unsigned Offset, MVT LocVT,
102                            LocInfo HTP) {
103    CCValAssign Ret;
104    Ret.ValNo = ValNo;
105    Ret.Loc = Offset;
106    Ret.isMem = true;
107    Ret.isCustom = false;
108    Ret.HTP = HTP;
109    Ret.ValVT = ValVT;
110    Ret.LocVT = LocVT;
111    return Ret;
112  }
113
114  static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT,
115                                  unsigned Offset, MVT LocVT,
116                                  LocInfo HTP) {
117    CCValAssign Ret;
118    Ret = getMem(ValNo, ValVT, Offset, LocVT, HTP);
119    Ret.isCustom = true;
120    return Ret;
121  }
122
123  // There is no need to differentiate between a pending CCValAssign and other
124  // kinds, as they are stored in a different list.
125  static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT,
126                                LocInfo HTP, unsigned ExtraInfo = 0) {
127    return getReg(ValNo, ValVT, ExtraInfo, LocVT, HTP);
128  }
129
130  void convertToReg(unsigned RegNo) {
131    Loc = RegNo;
132    isMem = false;
133  }
134
135  void convertToMem(unsigned Offset) {
136    Loc = Offset;
137    isMem = true;
138  }
139
140  unsigned getValNo() const { return ValNo; }
141  MVT getValVT() const { return ValVT; }
142
143  bool isRegLoc() const { return !isMem; }
144  bool isMemLoc() const { return isMem; }
145
146  bool needsCustom() const { return isCustom; }
147
148  unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
149  unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; }
150  unsigned getExtraInfo() const { return Loc; }
151  MVT getLocVT() const { return LocVT; }
152
153  LocInfo getLocInfo() const { return HTP; }
154  bool isExtInLoc() const {
155    return (HTP == AExt || HTP == SExt || HTP == ZExt);
156  }
157
158  bool isUpperBitsInLoc() const {
159    return HTP == AExtUpper || HTP == SExtUpper || HTP == ZExtUpper;
160  }
161};
162
163/// Describes a register that needs to be forwarded from the prologue to a
164/// musttail call.
165struct ForwardedRegister {
166  ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT)
167      : VReg(VReg), PReg(PReg), VT(VT) {}
168  unsigned VReg;
169  MCPhysReg PReg;
170  MVT VT;
171};
172
173/// CCAssignFn - This function assigns a location for Val, updating State to
174/// reflect the change.  It returns 'true' if it failed to handle Val.
175typedef bool CCAssignFn(unsigned ValNo, MVT ValVT,
176                        MVT LocVT, CCValAssign::LocInfo LocInfo,
177                        ISD::ArgFlagsTy ArgFlags, CCState &State);
178
179/// CCCustomFn - This function assigns a location for Val, possibly updating
180/// all args to reflect changes and indicates if it handled it. It must set
181/// isCustom if it handles the arg and returns true.
182typedef bool CCCustomFn(unsigned &ValNo, MVT &ValVT,
183                        MVT &LocVT, CCValAssign::LocInfo &LocInfo,
184                        ISD::ArgFlagsTy &ArgFlags, CCState &State);
185
186/// ParmContext - This enum tracks whether calling convention lowering is in
187/// the context of prologue or call generation. Not all backends make use of
188/// this information.
189typedef enum { Unknown, Prologue, Call } ParmContext;
190
191/// CCState - This class holds information needed while lowering arguments and
192/// return values.  It captures which registers are already assigned and which
193/// stack slots are used.  It provides accessors to allocate these values.
194class CCState {
195private:
196  CallingConv::ID CallingConv;
197  bool IsVarArg;
198  bool AnalyzingMustTailForwardedRegs = false;
199  MachineFunction &MF;
200  const TargetRegisterInfo &TRI;
201  SmallVectorImpl<CCValAssign> &Locs;
202  LLVMContext &Context;
203
204  unsigned StackOffset;
205  unsigned MaxStackArgAlign;
206  SmallVector<uint32_t, 16> UsedRegs;
207  SmallVector<CCValAssign, 4> PendingLocs;
208
209  // ByValInfo and SmallVector<ByValInfo, 4> ByValRegs:
210  //
211  // Vector of ByValInfo instances (ByValRegs) is introduced for byval registers
212  // tracking.
213  // Or, in another words it tracks byval parameters that are stored in
214  // general purpose registers.
215  //
216  // For 4 byte stack alignment,
217  // instance index means byval parameter number in formal
218  // arguments set. Assume, we have some "struct_type" with size = 4 bytes,
219  // then, for function "foo":
220  //
221  // i32 foo(i32 %p, %struct_type* %r, i32 %s, %struct_type* %t)
222  //
223  // ByValRegs[0] describes how "%r" is stored (Begin == r1, End == r2)
224  // ByValRegs[1] describes how "%t" is stored (Begin == r3, End == r4).
225  //
226  // In case of 8 bytes stack alignment,
227  // ByValRegs may also contain information about wasted registers.
228  // In function shown above, r3 would be wasted according to AAPCS rules.
229  // And in that case ByValRegs[1].Waste would be "true".
230  // ByValRegs vector size still would be 2,
231  // while "%t" goes to the stack: it wouldn't be described in ByValRegs.
232  //
233  // Supposed use-case for this collection:
234  // 1. Initially ByValRegs is empty, InRegsParamsProcessed is 0.
235  // 2. HandleByVal fillups ByValRegs.
236  // 3. Argument analysis (LowerFormatArguments, for example). After
237  // some byval argument was analyzed, InRegsParamsProcessed is increased.
238  struct ByValInfo {
239    ByValInfo(unsigned B, unsigned E, bool IsWaste = false) :
240      Begin(B), End(E), Waste(IsWaste) {}
241    // First register allocated for current parameter.
242    unsigned Begin;
243
244    // First after last register allocated for current parameter.
245    unsigned End;
246
247    // Means that current range of registers doesn't belong to any
248    // parameters. It was wasted due to stack alignment rules.
249    // For more information see:
250    // AAPCS, 5.5 Parameter Passing, Stage C, C.3.
251    bool Waste;
252  };
253  SmallVector<ByValInfo, 4 > ByValRegs;
254
255  // InRegsParamsProcessed - shows how many instances of ByValRegs was proceed
256  // during argument analysis.
257  unsigned InRegsParamsProcessed;
258
259protected:
260  ParmContext CallOrPrologue;
261
262public:
263  CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
264          SmallVectorImpl<CCValAssign> &locs, LLVMContext &C);
265
266  void addLoc(const CCValAssign &V) {
267    Locs.push_back(V);
268  }
269
270  LLVMContext &getContext() const { return Context; }
271  MachineFunction &getMachineFunction() const { return MF; }
272  CallingConv::ID getCallingConv() const { return CallingConv; }
273  bool isVarArg() const { return IsVarArg; }
274
275  /// getNextStackOffset - Return the next stack offset such that all stack
276  /// slots satisfy their alignment requirements.
277  unsigned getNextStackOffset() const {
278    return StackOffset;
279  }
280
281  /// getAlignedCallFrameSize - Return the size of the call frame needed to
282  /// be able to store all arguments and such that the alignment requirement
283  /// of each of the arguments is satisfied.
284  unsigned getAlignedCallFrameSize() const {
285    return alignTo(StackOffset, MaxStackArgAlign);
286  }
287
288  /// isAllocated - Return true if the specified register (or an alias) is
289  /// allocated.
290  bool isAllocated(unsigned Reg) const {
291    return UsedRegs[Reg/32] & (1 << (Reg&31));
292  }
293
294  /// AnalyzeFormalArguments - Analyze an array of argument values,
295  /// incorporating info about the formals into this state.
296  void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
297                              CCAssignFn Fn);
298
299  /// AnalyzeReturn - Analyze the returned values of a return,
300  /// incorporating info about the result values into this state.
301  void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
302                     CCAssignFn Fn);
303
304  /// CheckReturn - Analyze the return values of a function, returning
305  /// true if the return can be performed without sret-demotion, and
306  /// false otherwise.
307  bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
308                   CCAssignFn Fn);
309
310  /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
311  /// incorporating info about the passed values into this state.
312  void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
313                           CCAssignFn Fn);
314
315  /// AnalyzeCallOperands - Same as above except it takes vectors of types
316  /// and argument flags.
317  void AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
318                           SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
319                           CCAssignFn Fn);
320
321  /// AnalyzeCallResult - Analyze the return values of a call,
322  /// incorporating info about the passed values into this state.
323  void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
324                         CCAssignFn Fn);
325
326  /// AnalyzeCallResult - Same as above except it's specialized for calls which
327  /// produce a single value.
328  void AnalyzeCallResult(MVT VT, CCAssignFn Fn);
329
330  /// getFirstUnallocated - Return the index of the first unallocated register
331  /// in the set, or Regs.size() if they are all allocated.
332  unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const {
333    for (unsigned i = 0; i < Regs.size(); ++i)
334      if (!isAllocated(Regs[i]))
335        return i;
336    return Regs.size();
337  }
338
339  /// AllocateReg - Attempt to allocate one register.  If it is not available,
340  /// return zero.  Otherwise, return the register, marking it and any aliases
341  /// as allocated.
342  unsigned AllocateReg(unsigned Reg) {
343    if (isAllocated(Reg)) return 0;
344    MarkAllocated(Reg);
345    return Reg;
346  }
347
348  /// Version of AllocateReg with extra register to be shadowed.
349  unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
350    if (isAllocated(Reg)) return 0;
351    MarkAllocated(Reg);
352    MarkAllocated(ShadowReg);
353    return Reg;
354  }
355
356  /// AllocateReg - Attempt to allocate one of the specified registers.  If none
357  /// are available, return zero.  Otherwise, return the first one available,
358  /// marking it and any aliases as allocated.
359  unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) {
360    unsigned FirstUnalloc = getFirstUnallocated(Regs);
361    if (FirstUnalloc == Regs.size())
362      return 0;    // Didn't find the reg.
363
364    // Mark the register and any aliases as allocated.
365    unsigned Reg = Regs[FirstUnalloc];
366    MarkAllocated(Reg);
367    return Reg;
368  }
369
370  /// AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive
371  /// registers. If this is not possible, return zero. Otherwise, return the first
372  /// register of the block that were allocated, marking the entire block as allocated.
373  unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) {
374    if (RegsRequired > Regs.size())
375      return 0;
376
377    for (unsigned StartIdx = 0; StartIdx <= Regs.size() - RegsRequired;
378         ++StartIdx) {
379      bool BlockAvailable = true;
380      // Check for already-allocated regs in this block
381      for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
382        if (isAllocated(Regs[StartIdx + BlockIdx])) {
383          BlockAvailable = false;
384          break;
385        }
386      }
387      if (BlockAvailable) {
388        // Mark the entire block as allocated
389        for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
390          MarkAllocated(Regs[StartIdx + BlockIdx]);
391        }
392        return Regs[StartIdx];
393      }
394    }
395    // No block was available
396    return 0;
397  }
398
399  /// Version of AllocateReg with list of registers to be shadowed.
400  unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) {
401    unsigned FirstUnalloc = getFirstUnallocated(Regs);
402    if (FirstUnalloc == Regs.size())
403      return 0;    // Didn't find the reg.
404
405    // Mark the register and any aliases as allocated.
406    unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
407    MarkAllocated(Reg);
408    MarkAllocated(ShadowReg);
409    return Reg;
410  }
411
412  /// AllocateStack - Allocate a chunk of stack space with the specified size
413  /// and alignment.
414  unsigned AllocateStack(unsigned Size, unsigned Align) {
415    assert(Align && ((Align - 1) & Align) == 0); // Align is power of 2.
416    StackOffset = alignTo(StackOffset, Align);
417    unsigned Result = StackOffset;
418    StackOffset += Size;
419    MaxStackArgAlign = std::max(Align, MaxStackArgAlign);
420    ensureMaxAlignment(Align);
421    return Result;
422  }
423
424  void ensureMaxAlignment(unsigned Align) {
425    if (!AnalyzingMustTailForwardedRegs)
426      MF.getFrameInfo()->ensureMaxAlignment(Align);
427  }
428
429  /// Version of AllocateStack with extra register to be shadowed.
430  unsigned AllocateStack(unsigned Size, unsigned Align, unsigned ShadowReg) {
431    MarkAllocated(ShadowReg);
432    return AllocateStack(Size, Align);
433  }
434
435  /// Version of AllocateStack with list of extra registers to be shadowed.
436  /// Note that, unlike AllocateReg, this shadows ALL of the shadow registers.
437  unsigned AllocateStack(unsigned Size, unsigned Align,
438                         ArrayRef<MCPhysReg> ShadowRegs) {
439    for (unsigned i = 0; i < ShadowRegs.size(); ++i)
440      MarkAllocated(ShadowRegs[i]);
441    return AllocateStack(Size, Align);
442  }
443
444  // HandleByVal - Allocate a stack slot large enough to pass an argument by
445  // value. The size and alignment information of the argument is encoded in its
446  // parameter attribute.
447  void HandleByVal(unsigned ValNo, MVT ValVT,
448                   MVT LocVT, CCValAssign::LocInfo LocInfo,
449                   int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
450
451  // Returns count of byval arguments that are to be stored (even partly)
452  // in registers.
453  unsigned getInRegsParamsCount() const { return ByValRegs.size(); }
454
455  // Returns count of byval in-regs arguments proceed.
456  unsigned getInRegsParamsProcessed() const { return InRegsParamsProcessed; }
457
458  // Get information about N-th byval parameter that is stored in registers.
459  // Here "ByValParamIndex" is N.
460  void getInRegsParamInfo(unsigned InRegsParamRecordIndex,
461                          unsigned& BeginReg, unsigned& EndReg) const {
462    assert(InRegsParamRecordIndex < ByValRegs.size() &&
463           "Wrong ByVal parameter index");
464
465    const ByValInfo& info = ByValRegs[InRegsParamRecordIndex];
466    BeginReg = info.Begin;
467    EndReg = info.End;
468  }
469
470  // Add information about parameter that is kept in registers.
471  void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd) {
472    ByValRegs.push_back(ByValInfo(RegBegin, RegEnd));
473  }
474
475  // Goes either to next byval parameter (excluding "waste" record), or
476  // to the end of collection.
477  // Returns false, if end is reached.
478  bool nextInRegsParam() {
479    unsigned e = ByValRegs.size();
480    if (InRegsParamsProcessed < e)
481      ++InRegsParamsProcessed;
482    return InRegsParamsProcessed < e;
483  }
484
485  // Clear byval registers tracking info.
486  void clearByValRegsInfo() {
487    InRegsParamsProcessed = 0;
488    ByValRegs.clear();
489  }
490
491  // Rewind byval registers tracking info.
492  void rewindByValRegsInfo() {
493    InRegsParamsProcessed = 0;
494  }
495
496  ParmContext getCallOrPrologue() const { return CallOrPrologue; }
497
498  // Get list of pending assignments
499  SmallVectorImpl<llvm::CCValAssign> &getPendingLocs() {
500    return PendingLocs;
501  }
502
503  /// Compute the remaining unused register parameters that would be used for
504  /// the given value type. This is useful when varargs are passed in the
505  /// registers that normal prototyped parameters would be passed in, or for
506  /// implementing perfect forwarding.
507  void getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, MVT VT,
508                                   CCAssignFn Fn);
509
510  /// Compute the set of registers that need to be preserved and forwarded to
511  /// any musttail calls.
512  void analyzeMustTailForwardedRegisters(
513      SmallVectorImpl<ForwardedRegister> &Forwards, ArrayRef<MVT> RegParmTypes,
514      CCAssignFn Fn);
515
516  /// Returns true if the results of the two calling conventions are compatible.
517  /// This is usually part of the check for tailcall eligibility.
518  static bool resultsCompatible(CallingConv::ID CalleeCC,
519                                CallingConv::ID CallerCC, MachineFunction &MF,
520                                LLVMContext &C,
521                                const SmallVectorImpl<ISD::InputArg> &Ins,
522                                CCAssignFn CalleeFn, CCAssignFn CallerFn);
523
524private:
525  /// MarkAllocated - Mark a register and all of its aliases as allocated.
526  void MarkAllocated(unsigned Reg);
527};
528
529
530
531} // end namespace llvm
532
533#endif
534