Searched defs:iview (Results 1 - 13 of 13) sorted by relevance

/external/mesa3d/src/amd/vulkan/
H A Dradv_meta_decompress.c386 struct radv_image_view iview; local
388 radv_image_view_init(&iview, cmd_buffer->device,
410 radv_image_view_to_handle(&iview)
H A Dradv_meta_fast_clear.c426 struct radv_image_view iview; local
427 radv_image_view_init(&iview, cmd_buffer->device,
448 radv_image_view_to_handle(&iview)
H A Dradv_meta_blit2d.c57 struct radv_image_view *iview, VkFormat depth_format)
66 radv_image_view_init(iview, cmd_buffer->device,
106 struct radv_image_view iview; member in struct:blit2d_src_temps
148 create_iview(cmd_buffer, src_img, VK_IMAGE_USAGE_SAMPLED_BIT, &tmp->iview,
168 .imageView = radv_image_view_to_handle(&tmp->iview),
193 struct radv_image_view iview; member in struct:blit2d_dst_temps
213 &tmp->iview, depth_format);
220 radv_image_view_to_handle(&tmp->iview),
359 unsigned fs_key = radv_format_meta_fs_key(dst_temps.iview.vk_format);
54 create_iview(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *surf, VkImageUsageFlags usage, struct radv_image_view *iview, VkFormat depth_format) argument
H A Dradv_meta_bufimage.c845 struct radv_image_view *iview)
848 radv_image_view_init(iview, cmd_buffer->device,
842 create_iview(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *surf, VkImageUsageFlags usage, struct radv_image_view *iview) argument
H A Dradv_image.c753 radv_image_view_init(struct radv_image_view *iview, argument
775 iview->image = image;
776 iview->bo = image->bo;
777 iview->type = pCreateInfo->viewType;
778 iview->vk_format = pCreateInfo->format;
779 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
781 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
783 iview->vk_format = vk_format_stencil_only(iview->vk_format);
784 } else if (iview
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H A Dradv_meta_clear.c382 const struct radv_image_view *iview = fb->attachments[pass_att].attachment; local
383 const uint32_t samples = iview->image->samples;
385 unsigned fs_key = radv_format_meta_fs_key(iview->vk_format);
613 static bool depth_view_can_fast_clear(const struct radv_image_view *iview, argument
618 clear_rect->rect.extent.width != iview->extent.width ||
619 clear_rect->rect.extent.height != iview->extent.height)
621 if (iview->image->htile.size &&
622 iview->base_mip == 0 &&
623 iview->base_layer == 0 &&
624 radv_layout_can_expclear(iview
631 pick_depthstencil_pipeline(struct radv_meta_state *meta_state, const struct radv_image_view *iview, int samples_log2, VkImageAspectFlags aspects, VkImageLayout layout, const VkClearRect *clear_rect, VkClearDepthStencilValue clear_value) argument
671 const struct radv_image_view *iview = fb->attachments[pass_att].attachment; local
836 const struct radv_image_view *iview = fb->attachments[pass_att].attachment; local
1023 struct radv_image_view iview; local
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H A Dradv_device.c1583 struct radv_image_view *iview)
1590 const struct radeon_surf *surf = &iview->image->surface;
1591 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
1593 desc = vk_format_description(iview->vk_format);
1597 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1602 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1603 va += iview->image->cmask.offset;
1605 cb->cb_color_cmask_slice = iview
1581 radv_initialise_color_surface(struct radv_device *device, struct radv_color_buffer_info *cb, struct radv_image_view *iview) argument
1724 radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_info *ds, struct radv_image_view *iview) argument
1862 struct radv_image_view *iview = radv_image_view_from_handle(_iview); local
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/external/mesa3d/src/gallium/drivers/softpipe/
H A Dsp_image.c36 const struct pipe_image_view *iview,
42 return iview->u.buf.offset;
49 base_layer = r_coord + iview->u.tex.first_layer;
50 return softpipe_get_tex_image_offset(spr, iview->u.tex.level, base_layer);
147 get_dimensions(const struct pipe_image_view *iview, argument
156 *width = iview->u.buf.size / util_format_get_blocksize(pformat);
169 level = spr->base.target == PIPE_BUFFER ? 0 : iview->u.tex.level;
212 struct pipe_image_view *iview; local
222 iview = &sp_img->sp_iview[params->unit];
223 spr = (struct softpipe_resource *)iview
35 get_image_offset(const struct softpipe_resource *spr, const struct pipe_image_view *iview, enum pipe_format format, unsigned r_coord) argument
314 struct pipe_image_view *iview; local
381 handle_op_uint(const struct pipe_image_view *iview, const struct tgsi_image_params *params, bool just_read, char *data_ptr, uint qi, unsigned stride, unsigned opcode, int s, int t, float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE], float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE]) argument
498 handle_op_int(const struct pipe_image_view *iview, const struct tgsi_image_params *params, bool just_read, char *data_ptr, uint qi, unsigned stride, unsigned opcode, int s, int t, float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE], float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE]) argument
612 handle_op_r32f_xchg(const struct pipe_image_view *iview, const struct tgsi_image_params *params, bool just_read, char *data_ptr, uint qi, unsigned stride, unsigned opcode, int s, int t, float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE]) argument
661 struct pipe_image_view *iview; local
743 struct pipe_image_view *iview; local
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/external/mesa3d/src/intel/vulkan/
H A Danv_dump.c422 struct anv_image_view *iview = fb->attachments[i]; local
425 for_each_bit(b, iview->image->aspects) {
439 dump_add_image(cmd_buffer, (struct anv_image *)iview->image, aspect,
440 iview->isl.base_level, iview->isl.base_array_layer,
H A Danv_image.c472 struct anv_image_view *iview; local
474 iview = vk_alloc2(&device->alloc, pAllocator, sizeof(*iview), 8,
476 if (iview == NULL)
504 iview->image = image;
505 iview->bo = image->bo;
506 iview->offset = image->offset + surface->offset;
508 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
509 iview->vk_format = pCreateInfo->format;
514 iview
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H A Danv_cmd_buffer.c813 const struct anv_image_view *iview = local
816 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT |
819 return iview;
H A Danv_blorp.c1198 struct anv_image_view *iview = fb->attachments[a]; local
1199 const struct anv_image *image = iview->image;
1226 blorp_fast_clear(&batch, &surf, iview->isl.format,
1227 iview->isl.base_level,
1228 iview->isl.base_array_layer, fb->layers,
1236 blorp_clear(&batch, &surf, iview->isl.format, iview->isl.swizzle,
1237 iview->isl.base_level,
1238 iview->isl.base_array_layer, fb->layers,
1262 const struct anv_image_view *iview local
1446 struct anv_image_view *iview = fb->attachments[att]; local
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H A DgenX_cmd_buffer.c168 const struct anv_image_view *iview,
176 iview->bo, iview->offset);
179 uint32_t aux_offset = iview->offset + iview->image->aux_surface.offset;
191 iview->bo, aux_offset);
216 struct anv_image_view *iview,
220 if (iview->image->aux_surface.isl.size == 0) {
227 assert(iview->image->aux_surface.isl.usage & ISL_SURF_USAGE_CCS_BIT);
230 color_is_zero_one(att_state->clear_value.color, iview
167 add_image_view_relocs(struct anv_cmd_buffer *cmd_buffer, const struct anv_image_view *iview, enum isl_aux_usage aux_usage, struct anv_state state) argument
214 color_attachment_compute_aux_usage(struct anv_device *device, struct anv_attachment_state *att_state, struct anv_image_view *iview, VkRect2D render_area, union isl_color_value *fast_clear_color) argument
519 struct anv_image_view *iview = framebuffer->attachments[i]; local
2178 const struct anv_image_view *iview = local
2340 const struct anv_image_view *iview = local
2387 const struct anv_image_view *iview = local
2410 const struct anv_image_view *iview = local
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