Searched defs:lis (Results 1 - 25 of 28) sorted by relevance

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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
H A DCalcSpillWeights.h48 VirtRegAuxInfo(MachineFunction &mf, LiveIntervals &lis, argument
50 MF(mf), LIS(lis), Loops(loops) {}
/external/llvm/include/llvm/CodeGen/
H A DCalcSpillWeights.h62 VirtRegAuxInfo(MachineFunction &mf, LiveIntervals &lis, argument
66 : MF(mf), LIS(lis), VRM(vrm), Loops(loops), MBFI(mbfi), normalize(norm) {}
H A DLiveRangeEdit.h120 /// @param lis The collection of all live intervals in this function.
127 MachineFunction &MF, LiveIntervals &lis, VirtRegMap *vrm,
130 : Parent(parent), NewRegs(newRegs), MRI(MF.getRegInfo()), LIS(lis),
126 LiveRangeEdit(LiveInterval *parent, SmallVectorImpl<unsigned> &newRegs, MachineFunction &MF, LiveIntervals &lis, VirtRegMap *vrm, Delegate *delegate = nullptr, SmallPtrSet<MachineInstr *, 32> *deadRemats = nullptr) argument
/external/llvm/lib/CodeGen/
H A DRegAllocBase.cpp55 LiveIntervals &lis,
60 LIS = &lis;
54 init(VirtRegMap &vrm, LiveIntervals &lis, LiveRegMatrix &mat) argument
H A DInterferenceCache.cpp46 LiveIntervals *lis,
53 Entries[i].clear(mf, indexes, lis);
43 init(MachineFunction *mf, LiveIntervalUnion *liuarray, SlotIndexes *indexes, LiveIntervals *lis, const TargetRegisterInfo *tri) argument
H A DInterferenceCache.h99 void clear(MachineFunction *mf, SlotIndexes *indexes, LiveIntervals *lis) { argument
104 LIS = lis;
H A DRegisterPressure.cpp222 const LiveIntervals *lis,
237 assert(lis && "IntervalPressure requires LiveIntervals");
238 LIS = lis;
220 init(const MachineFunction *mf, const RegisterClassInfo *rci, const LiveIntervals *lis, const MachineBasicBlock *mbb, MachineBasicBlock::const_iterator pos, bool TrackLaneMasks, bool TrackUntiedDefs) argument
H A DSplitKit.cpp44 InsertPointAnalysis::InsertPointAnalysis(const LiveIntervals &lis, argument
46 : LIS(lis), LastInsertPoint(BBNum) {}
124 SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis, argument
126 : MF(vrm.getMachineFunction()), VRM(vrm), LIS(lis), Loops(mli),
128 IPA(lis, MF.getNumBlockIDs()) {}
342 LiveIntervals &lis, VirtRegMap &vrm,
345 : SA(sa), AA(aa), LIS(lis), VRM(vrm),
341 SplitEditor(SplitAnalysis &sa, AliasAnalysis &aa, LiveIntervals &lis, VirtRegMap &vrm, MachineDominatorTree &mdt, MachineBlockFrequencyInfo &mbfi) argument
H A DRegisterCoalescer.cpp1865 LiveIntervals *lis, const TargetRegisterInfo *TRI, bool SubRangeJoin,
1869 NewVNInfo(newVNInfo), CP(cp), LIS(lis), Indexes(LIS->getSlotIndexes()),
1863 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask, SmallVectorImpl<VNInfo*> &newVNInfo, const CoalescerPair &cp, LiveIntervals *lis, const TargetRegisterInfo *TRI, bool SubRangeJoin, bool TrackSubRegLiveness) argument
H A DMachinePipeliner.cpp261 SwingSchedulerDAG(MachinePipeliner &P, MachineLoop &L, LiveIntervals &lis, argument
264 Scheduled(false), Loop(L), LIS(lis), RegClassInfo(rci),
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DSplitter.h53 LiveIntervals *lis; member in class:llvm::LoopSplitter
H A DCalcSpillWeights.cpp48 LiveIntervals &lis = getAnalysis<LiveIntervals>(); local
49 VirtRegAuxInfo vrai(fn, lis, getAnalysis<MachineLoopInfo>());
50 for (LiveIntervals::iterator I = lis.begin(), E = lis.end(); I != E; ++I) {
H A DLiveRangeEdit.cpp56 void LiveRangeEdit::scanRemattable(LiveIntervals &lis, argument
64 MachineInstr *DefMI = lis.getInstructionFromIndex(VNI->def);
72 bool LiveRangeEdit::anyRematerializable(LiveIntervals &lis, argument
76 scanRemattable(lis, tii, aa);
85 LiveIntervals &lis) {
93 if (MO.isUndef() || !lis.hasInterval(MO.getReg()))
101 LiveInterval &li = lis.getInterval(MO.getReg());
114 LiveIntervals &lis) {
124 DefIdx = lis.getInstructionIndex(RM.OrigMI);
127 RM.OrigMI = lis
82 allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx, SlotIndex UseIdx, LiveIntervals &lis) argument
111 canRematerializeAt(Remat &RM, SlotIndex UseIdx, bool cheapAsAMove, LiveIntervals &lis) argument
142 rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const Remat &RM, LiveIntervals &lis, const TargetInstrInfo &tii, const TargetRegisterInfo &tri, bool Late) argument
[all...]
H A DSpiller.cpp56 LiveIntervals *lis; member in class:__anon19882::SpillerBase
66 lis = &pass.getAnalysis<LiveIntervals>();
122 LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
143 lis->InsertMachineInstrInMaps(loadInstr).getDefIndex();
147 newLI->getNextValue(loadIndex, 0, lis->getVNInfoAllocator());
157 lis->InsertMachineInstrInMaps(storeInstr).getDefIndex();
161 newLI->getNextValue(beginIndex, 0, lis->getVNInfoAllocator());
197 LiveIntervals *lis; member in class:__anon19884::StandardSpiller
205 lis(&pass.getAnalysis<LiveIntervals>()),
213 lis
[all...]
H A DRegAllocBasic.cpp230 void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) { argument
235 LIS = &lis;
H A DRenderMachineFunction.h63 LiveIntervals *lis, const RenderMachineFunction *rmf);
119 LiveIntervals *lis; member in class:llvm::MFRenderingOptions
142 const TargetRegisterInfo *tri, LiveIntervals *lis);
171 LiveIntervals *lis; member in class:llvm::TargetRegisterExtraInfo
248 LiveIntervals *lis; member in class:llvm::RenderMachineFunction
H A DSplitter.cpp45 StartSlotComparator(LiveIntervals &lis) : lis(lis) {} argument
48 return lis.getMBBStartIdx(mbb1) < lis.getMBBStartIdx(mbb2);
51 LiveIntervals &lis; member in class:llvm::StartSlotComparator
101 newLI = &ls.lis->getOrCreateInterval(vreg);
111 ls.lis->getVNInfoAllocator());
131 ls.lis->findExitingRange(li, preHeader);
142 ls.lis
[all...]
H A DRegAllocPBQP.cpp135 LiveIntervals *lis; member in class:__anon19846::RegAllocPBQP
193 const LiveIntervals *lis,
207 for (LiveIntervals::const_iterator itr = lis->begin(), end = lis->end();
222 const LiveInterval *vregLI = &lis->getInterval(vreg);
240 const LiveInterval *pregLI = &lis->getInterval(preg);
288 const LiveInterval &l1 = lis->getInterval(vr1);
294 const LiveInterval &l2 = lis->getInterval(vr2);
339 const LiveIntervals *lis,
343 std::auto_ptr<PBQPRAProblem> p = PBQPBuilder::build(mf, lis, loopInf
192 build(MachineFunction *mf, const LiveIntervals *lis, const MachineLoopInfo *loopInfo, const RegSet &vregs) argument
337 build( MachineFunction *mf, const LiveIntervals *lis, const MachineLoopInfo *loopInfo, const RegSet &vregs) argument
[all...]
H A DRenderMachineFunction.cpp196 LiveIntervals *lis,
200 this->lis = lis;
269 for (LiveIntervals::iterator liItr = lis->begin(), liEnd = lis->end();
296 if (lis->hasInterval(reg)) {
297 intervalSet.insert(&lis->getInterval(reg));
316 LiveIntervals *lis) {
320 this->lis = lis;
194 setup(MachineFunction *mf, const TargetRegisterInfo *tri, LiveIntervals *lis, const RenderMachineFunction *rmf) argument
313 setup(MachineFunction *mf, MachineRegisterInfo *mri, const TargetRegisterInfo *tri, LiveIntervals *lis) argument
[all...]
H A DSplitKit.cpp43 const LiveIntervals &lis,
47 LIS(lis),
303 LiveIntervals &lis,
306 : SA(sa), LIS(lis), VRM(vrm),
42 SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis, const MachineLoopInfo &mli) argument
302 SplitEditor(SplitAnalysis &sa, LiveIntervals &lis, VirtRegMap &vrm, MachineDominatorTree &mdt) argument
/external/v8/src/ppc/
H A Dassembler-ppc.cc149 // coded. Being specially coded on PPC means that it is a lis/ori
332 // This code assumes a FIXED_SEQUENCE for 64bit loads (lis/ori)
336 // 3d800000 lis r12, 0
346 // This code assumes a FIXED_SEQUENCE for 32bit loads (lis/ori)
349 // 3d802553 lis r12, 9555
972 DCHECK(!src.is(r0)); // use lis instead to show intent
1130 void Assembler::lis(Register dst, const Operand& imm) { function in class:v8::internal::Assembler
1701 lis(dst, Operand(value >> 16));
1707 lis(dst, Operand(value >> 48));
1743 lis(ds
[all...]
/external/svox/pico/lib/
H A Dpicopr.c783 picoos_bool lis; local
790 lis = TRUE;
792 while (lis && (li < PR_MAX_DATA_LEN) && (str[li] != 0)) {
802 lis = lis && picobase_is_utf8_uppercase(lutf,PICOBASE_UTF8_MAXLEN+1);
804 lis = lis && picobase_is_utf8_lowercase(lutf,PICOBASE_UTF8_MAXLEN+1);
808 return lis;
/external/robolectric/v3/runtime/
H A Dandroid-all-4.1.2_r1-robolectric-0.jarMETA-INF/ META-INF/MANIFEST.MF android/ android/accessibilityservice/ android/accessibilityservice/AccessibilityService$1.class ...
H A Dandroid-all-4.2.2_r1.2-robolectric-0.jarMETA-INF/ META-INF/MANIFEST.MF android/ android/accessibilityservice/ android/accessibilityservice/AccessibilityService$1.class ...
H A Dandroid-all-4.3_r2-robolectric-0.jarMETA-INF/ META-INF/MANIFEST.MF android/ android/accessibilityservice/ android/accessibilityservice/AccessibilityService$1.class ...

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