| /external/llvm/test/MC/ARM/ |
| H A D | arm-arithmetic-aliases.s | 36 orr r2, r2, #6 label
37 orr r2, #6 label
38 orr r2, r2, r3 label
39 orr r2, r3 label
41 @ CHECK: orr r2, r2, #6 @ encoding: [0x06,0x20,0x82,0xe3]
42 @ CHECK: orr r2, r2, #6 @ encoding: [0x06,0x20,0x82,0xe3]
43 @ CHECK: orr r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe1]
44 @ CHECK: orr r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe1]
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| H A D | arm-arithmetic-aliases.s | 36 orr r2, r2, #6 label
37 orr r2, #6 label
38 orr r2, r2, r3 label
39 orr r2, r3 label
41 @ CHECK: orr r2, r2, #6 @ encoding: [0x06,0x20,0x82,0xe3]
42 @ CHECK: orr r2, r2, #6 @ encoding: [0x06,0x20,0x82,0xe3]
43 @ CHECK: orr r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe1]
44 @ CHECK: orr r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe1]
|
| /external/llvm/test/MC/AArch64/ |
| H A D | arm64-diags.s | 258 orr w0, w0, w0, lsl #32 label
260 ; CHECK-ERRORS: orr w0, w0, w0, lsl #32
|
| /external/boringssl/src/crypto/curve25519/asm/ |
| H A D | x25519-asm-arm.S | 79 orr r6,r6,#64 label
|
| /external/vixl/src/aarch64/ |
| H A D | assembler-aarch64.cc | 526 void Assembler::orr(const Register& rd, function in class:vixl::aarch64::Assembler
2034 // second operand of zero. Otherwise, orr with first operand zr is
2039 orr(rd, AppropriateZeroRegFor(rd), rm);
2688 V(orr, NEON_ORR, vd.Is8B() || vd.Is16B()) \
2800 void Assembler::orr(const VRegister& vd, const int imm8, const int left_shift) {
2808 orr(vd.V8B(), vn.V8B(), vn.V8B());
2811 orr(vd.V16B(), vn.V16B(), vn.V16B());
|
| H A D | logic-aarch64.cc | 1229 LogicVRegister Simulator::orr(VectorFormat vform, function in class:vixl::aarch64::Simulator
2493 LogicVRegister Simulator::orr(VectorFormat vform, function in class:vixl::aarch64::Simulator
|
| /external/v8/src/arm64/ |
| H A D | assembler-arm64.cc | 1221 void Assembler::orr(const Register& rd, function in class:v8::internal::Assembler
1777 // second operand of zero. Otherwise, orr with first operand zr is
1782 orr(rd, AppropriateZeroRegFor(rd), rm);
|
| /external/skia/tests/ |
| H A D | PathTest.cpp | 4774 SkRRect orr; local
4775 orr.setRectRadii(ro, rdo);
4776 SkMakeNullCanvas()->drawDRRect(orr, irr, SkPaint());
|
| /external/v8/src/arm/ |
| H A D | assembler-arm.cc | 934 // orr dst, dst, #target8_1 << 8
935 // orr dst, dst, #target8_2 << 16
963 // Patch with a sequence of mov/orr/orr instructions.
971 patcher.masm()->orr(dst, dst, Operand(target8_1 << 8));
976 patcher.masm()->orr(dst, dst, Operand(target8_1 << 8));
977 patcher.masm()->orr(dst, dst, Operand(target8_2 << 16));
1196 // A movw / movt or mov / orr immediate load.
1243 orr(target, target, Operand(imm32 & (kImm8Mask << 8)), LeaveCC, cond);
1244 orr(targe
1584 void Assembler::orr(Register dst, Register src1, const Operand& src2, function in class:v8::internal::Assembler
[all...] |
| /external/vixl/src/aarch32/ |
| H A D | assembler-aarch32.cc | 7125 void Assembler::orr(Condition cond, function in class:vixl::aarch32::Assembler
7206 Delegate(kOrr, &Assembler::orr, cond, size, rd, rn, operand);
|
| H A D | assembler-aarch32.h | 2653 void orr(Condition cond,
2658 void orr(Register rd, Register rn, const Operand& operand) { function in class:vixl::aarch32::Assembler
2659 orr(al, Best, rd, rn, operand);
2661 void orr(Condition cond, Register rd, Register rn, const Operand& operand) { function in class:vixl::aarch32::Assembler
2662 orr(cond, Best, rd, rn, operand);
2664 void orr(EncodingSize size, function in class:vixl::aarch32::Assembler
2668 orr(al, size, rd, rn, operand);
|
| H A D | disasm-aarch32.cc | 2012 void Disassembler::orr(Condition cond, function in class:vixl::aarch32::Disassembler
7637 orr(CurrentCond(),
8559 orr(CurrentCond(),
18401 orr(CurrentCond(),
18432 orr(CurrentCond(),
18443 orr(CurrentCond(),
[all...] |