Searched defs:src2 (Results 1 - 25 of 185) sorted by last modified time

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/external/wpa_supplicant_8/hostapd/src/utils/
H A D	common.c	725 const u8 *src2, size_t src2_len) 741 if (src2) { 743 os_memcpy(res + len, src2, res_len - len); 747 os_memcpy(res + len, src2, src2_len); 723 merge_byte_arrays(u8 *res, size_t res_len, const u8 *src1, size_t src1_len, const u8 *src2, size_t src2_len) argument
/external/wpa_supplicant_8/src/utils/
H A D	common.c	725 const u8 *src2, size_t src2_len) 741 if (src2) { 743 os_memcpy(res + len, src2, res_len - len); 747 os_memcpy(res + len, src2, src2_len); 723 merge_byte_arrays(u8 *res, size_t res_len, const u8 *src1, size_t src1_len, const u8 *src2, size_t src2_len) argument
/external/wpa_supplicant_8/wpa_supplicant/src/utils/
H A D	common.c	725 const u8 *src2, size_t src2_len) 741 if (src2) { 743 os_memcpy(res + len, src2, res_len - len); 747 os_memcpy(res + len, src2, src2_len); 723 merge_byte_arrays(u8 *res, size_t res_len, const u8 *src1, size_t src1_len, const u8 *src2, size_t src2_len) argument
/external/webp/src/dsp/
H A D	enc.c	736 const uint8_t* src2, int stride2, 747 src2 += ymin * stride2; 748 for (y = ymin; y <= ymax; ++y, src1 += stride1, src2 += stride2) { 753 const uint32_t s2 = src2[x]; 766 const uint8_t* src2, int stride2) { 769 for (y = 0; y <= 2 * VP8_SSIM_KERNEL; ++y, src1 += stride1, src2 += stride2) { 773 const uint32_t s2 = src2[x]; 787 const uint8_t* src2, int len) { 792 const int32_t diff = src1[i] - src2[i]; 735 SSIMGetClipped_C(const uint8_t* src1, int stride1, const uint8_t* src2, int stride2, int xo, int yo, int W, int H) argument 765 SSIMGet_C(const uint8_t* src1, int stride1, const uint8_t* src2, int stride2) argument 786 AccumulateSSE(const uint8_t* src1, const uint8_t* src2, int len) argument
H A D	enc_msa.c	713 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local 717 LD_UB8(a, BPS, src0, src1, src2, src3, src4, src5, src6, src7); 720 PACK_DPADD_UB4_SW(src2, ref2, src3, ref3, out0, out1, out2, out3); 725 LD_UB8(a, BPS, src0, src1, src2, src3, src4, src5, src6, src7); 728 PACK_DPADD_UB4_SW(src2, ref2, src3, ref3, out0, out1, out2, out3); 740 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local 744 LD_UB8(a, BPS, src0, src1, src2, src3, src4, src5, src6, src7); 747 PACK_DPADD_UB4_SW(src2, ref2, src3, ref3, out0, out1, out2, out3); 759 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local 764 LD_UB8(a, BPS, src0, src1, src2, src 779 uint32_t src0, src1, src2, src3, ref0, ref1, ref2, ref3; local [all...]
H A D	enc_sse2.c	299 const __m128i src2 = _mm_loadl_epi64((const __m128i*)&src[2 * BPS]); local 307 const __m128i src_1 = _mm_unpacklo_epi16(src2, src3); 343 const __m128i src2 = _mm_loadl_epi64((const __m128i*)&src[2 * BPS]); local 347 const __m128i src_2 = _mm_unpacklo_epi8(src2, zero); 389 const __m128i src2 = _mm_loadl_epi64((__m128i*)&in[2 * 16]); local 392 const __m128i A23 = _mm_unpacklo_epi16(src2, src3); // A2 A3 | ... 1373 const uint8_t* src2, int len) { 1382 __m128i b0 = _mm_loadu_si128((const __m128i*)&src2[i]); 1386 const __m128i b1 = _mm_loadu_si128((const __m128i*)&src2[i]); 1392 b0 = _mm_loadu_si128((const __m128i*)&src2[ 1372 AccumulateSSE_SSE2(const uint8_t* src1, const uint8_t* src2, int len) argument 1449 SSIMGet_SSE2(const uint8_t* src1, int stride1, const uint8_t* src2, int stride2) argument [all...]
H A D	rescaler_msa.c	124 v4u32 src0, src1, src2, src3; local 126 LD_UW4(frow, 4, src0, src1, src2, src3); 127 CALC_MULT_FIX_16(src0, src1, src2, src3, scale, shift, out); 137 v4u32 src0, src1, src2; local 138 LD_UW3(frow, 4, src0, src1, src2); 141 CALC_MULT_FIX_4(src2, scale, shift, val2_m); 275 v4u32 src0, src1, src2, src3, frac0, frac1, frac2, frac3; local 277 LD_UW4(frow, 4, src0, src1, src2, src3); 278 CALC_MULT_FIX1_16(src0, src1, src2, src3, y_scale, shiftval, 280 LD_UW4(irow, 4, src0, src1, src2, src 295 v4u32 src0, src1, src2, frac0, frac1, frac2; local 360 v4u32 src0, src1, src2, src3; local 374 v4u32 src0, src1, src2; local [all...]
/external/webp/src/enc/
H A D	picture_csp_enc.c	280 static void UpdateChroma(const fixed_y_t* src1, const fixed_y_t* src2, argument 285 src2[0 * uv_w + 0], src2[0 * uv_w + 1]); 287 src2[2 * uv_w + 0], src2[2 * uv_w + 1]); 289 src2[4 * uv_w + 0], src2[4 * uv_w + 1]); 296 src2 += 2; 479 fixed_y_t* const src2 = tmp_buffer + 3 * w; local 485 step, picture->width, src2); 517 fixed_y_t* const src2 = tmp_buffer + 3 * w; local [all...]
/external/vixl/src/aarch64/
H A D	logic-aarch64.cc	713 const LogicVRegister& src2, 718 int64_t sb = src2.Int(vform, i); 720 uint64_t ub = src2.Uint(vform, i); 768 const LogicVRegister& src2) { 772 uint64_t ub = src2.Uint(vform, i); 782 const LogicVRegister& src2) { 788 uint64_t ub = src2.UintLeftJustified(vform, i); 813 const LogicVRegister& src2) { 815 uzp1(vform, temp1, src1, src2); 816 uzp2(vform, temp2, src1, src2); 710 cmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument 765 cmptst(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 779 add(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 810 addp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 822 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 833 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 844 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 856 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 867 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 878 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 889 smull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 901 smull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 913 umull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 925 umull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 937 smlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 949 smlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 961 umlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 973 umlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 985 smlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 997 smlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1009 umlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1021 umlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1033 sqdmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1045 sqdmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1057 sqdmlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1069 sqdmlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1081 sqdmlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1093 sqdmlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1105 sqdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1116 sqrdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1139 pmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1153 pmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1169 pmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1186 sub(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1217 and_(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1229 orr(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1241 orn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1253 eor(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1265 bic(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1294 bif(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1310 bit(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1326 bsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1342 sminmax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) argument 1363 smax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1371 smin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1379 sminmaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) argument 1407 smaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1415 sminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1522 uminmax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) argument 1543 umax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1551 umin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1559 uminmaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) argument 1587 umaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1595 uminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1910 sshl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1970 ushl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2217 absdiff(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool issigned) argument 2238 saba(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2250 uaba(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2401 ext(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 2843 uaddl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2855 uaddl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2867 uaddw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2878 uaddw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2889 saddl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2901 saddl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2913 saddw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2924 saddw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2935 usubl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2947 usubl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2959 usubw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2970 usubw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2981 ssubl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2993 ssubl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3005 ssubw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3016 ssubw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3027 uabal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3039 uabal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3051 sabal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3063 sabal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3075 uabdl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3087 uabdl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3099 sabdl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3111 sabdl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3123 umull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3135 umull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3147 smull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3159 smull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3171 umlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3183 umlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3195 smlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3207 smlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3219 umlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3231 umlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3243 smlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3255 smlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3267 sqdmlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3277 sqdmlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3287 sqdmlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3297 sqdmlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3307 sqdmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3317 sqdmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3327 sqrdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool round) argument 3357 sqdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3365 addhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3370 add(VectorFormatDoubleWidth(vform), temp, src1, src2); local 3376 addhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3387 raddhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3392 add(VectorFormatDoubleWidth(vform), temp, src1, src2); local 3398 raddhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3409 subhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3414 sub(VectorFormatDoubleWidth(vform), temp, src1, src2); local 3420 subhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3431 rsubhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3436 sub(VectorFormatDoubleWidth(vform), temp, src1, src2); local 3442 rsubhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3453 trn1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3473 trn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3493 zip1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3513 zip2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3533 uzp1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3552 uzp2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3967 fnmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3978 frecps(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3993 frecps(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4008 frsqrts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4023 frsqrts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4038 fcmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument 4077 fcmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument 4109 fabscmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument 4130 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4146 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4161 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4177 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4247 fabd(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4351 fmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 4371 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 4391 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 4411 fmulx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument [all...]
H A D	macro-assembler-aarch64.cc	1887 const CPURegister& src2, 1890 VIXL_ASSERT(AreSameSizeAndType(src0, src1, src2, src3)); 1893 int count = 1 + src1.IsValid() + src2.IsValid() + src3.IsValid(); 1897 PushHelper(count, size, src0, src1, src2, src3); 2014 const CPURegister& src2, 2022 VIXL_ASSERT(AreSameSizeAndType(src0, src1, src2, src3)); 2029 VIXL_ASSERT(src1.IsNone() && src2.IsNone() && src3.IsNone()); 2033 VIXL_ASSERT(src2.IsNone() && src3.IsNone()); 2038 stp(src2, src1, MemOperand(StackPointer(), -3 * size, PreIndex)); 2045 stp(src3, src2, MemOperan 1885 Push(const CPURegister& src0, const CPURegister& src1, const CPURegister& src2, const CPURegister& src3) argument 2010 PushHelper(int count, int size, const CPURegister& src0, const CPURegister& src1, const CPURegister& src2, const CPURegister& src3) argument [all...]
/external/vixl/test/aarch32/
H A D	test-assembler-aarch32.cc	5161 const uint32_t src2[4] = {0x11111111, 0x22222222, 0x33333333, 0x44444444}; local 5170 __ Mov(r10, reinterpret_cast<uintptr_t>(src2 - 1)); 5188 ASSERT_EQUAL_32(reinterpret_cast<uintptr_t>(src2 + 1), r10);
/external/vboot_reference/firmware/stub/
H A D	utility_stub.c	20 int Memcmp(const void *src1, const void *src2, size_t n) argument 22 return memcmp(src1, src2, n);
/external/vboot_reference/tests/
H A D	stateful_util_tests.c	151 char* src2 = "Howserrr"; local 167 TEST_PTR_EQ(src2, StatefulMemcpy_r(&s, src2, 8), 224 char* src2 = "ThisIsOnlyATest"; local 246 StatefulInit(&s, src2, 16); 249 TEST_PTR_EQ(src2 + 16, s.remaining_buf, "StatefulMemcpy(all) buf"); 251 TEST_EQ(0, strcmp(src2, buf), "StatefulMemcpy(all) contents"); 257 TEST_PTR_EQ(src2 + 16, s.remaining_buf, "StatefulMemcpy(0) buf"); 259 TEST_EQ(0, strcmp(src2, buf), "StatefulMemcpy(0) contents"); 266 TEST_EQ(0, strcmp(src2, bu [all...]
/external/valgrind/none/tests/ppc32/
H A D	jm-insns.c	6322 unsigned int *src1, *src2, *dst; local 6363 src2 = (unsigned int*)&vec_in2; 6368 printf("%08x%08x%08x%08x\n", src2[0], src2[1], src2[2], src2[3]); 6388 unsigned int *src1, *src2, *src3, *dst; local 6432 src2 = (unsigned int*)&vec_in2; 6438 src2[0], src2[ 6463 unsigned int *src1, *src2, *dst; local 6661 unsigned int *src1, *src2, *dst; local 7088 unsigned int *src1, *src2, *dst; local 7155 unsigned int *src1, *src2, *src3, *dst; local [all...]
/external/valgrind/none/tests/ppc64/
H A D	jm-insns.c	6322 unsigned int *src1, *src2, *dst; local 6363 src2 = (unsigned int*)&vec_in2; 6368 printf("%08x%08x%08x%08x\n", src2[0], src2[1], src2[2], src2[3]); 6388 unsigned int *src1, *src2, *src3, *dst; local 6432 src2 = (unsigned int*)&vec_in2; 6438 src2[0], src2[ 6463 unsigned int *src1, *src2, *dst; local 6661 unsigned int *src1, *src2, *dst; local 7088 unsigned int *src1, *src2, *dst; local 7155 unsigned int *src1, *src2, *src3, *dst; local [all...]
/external/v8/src/s390/
H A D	macro-assembler-s390.cc	2776 DoubleRegister src2) { 2777 if (src2.is(d0)) { 2779 Move(d2, src2); 2783 Move(d2, src2); 3243 instr(dst, src2); \ 3248 const MemOperand& src2) { 3252 void MacroAssembler::MulHigh32(Register dst, Register src1, Register src2) { argument 3253 if (dst.is(src2)) { 3254 std::swap(src1, src2); 3260 const Operand& src2) { 2775 MovToFloatParameters(DoubleRegister src1, DoubleRegister src2) argument 3247 MulHigh32(Register dst, Register src1, const MemOperand& src2) argument 3259 MulHigh32(Register dst, Register src1, const Operand& src2) argument 3273 MulHighU32(Register dst, Register src1, const MemOperand& src2) argument 3278 MulHighU32(Register dst, Register src1, Register src2) argument 3282 MulHighU32(Register dst, Register src1, const Operand& src2) argument 3299 Mul32WithOverflowIfCCUnequal(Register dst, Register src1, const MemOperand& src2) argument 3307 Mul32WithOverflowIfCCUnequal(Register dst, Register src1, Register src2) argument 3315 Mul32WithOverflowIfCCUnequal(Register dst, Register src1, const Operand& src2) argument 3336 Mul(Register dst, Register src1, Register src2) argument 3368 Div32(Register dst, Register src1, const MemOperand& src2) argument 3373 Div32(Register dst, Register src1, Register src2) argument 3377 Div32(Register dst, Register src1, const Operand& src2) argument 3394 DivU32(Register dst, Register src1, const MemOperand& src2) argument 3399 DivU32(Register dst, Register src1, Register src2) argument 3403 DivU32(Register dst, Register src1, const Operand& src2) argument 3419 Mod32(Register dst, Register src1, const MemOperand& src2) argument 3424 Mod32(Register dst, Register src1, Register src2) argument 3428 Mod32(Register dst, Register src1, const Operand& src2) argument 3445 ModU32(Register dst, Register src1, const MemOperand& src2) argument 3450 ModU32(Register dst, Register src1, Register src2) argument 3454 ModU32(Register dst, Register src1, const Operand& src2) argument 3479 MulPWithCondition(Register dst, Register src1, Register src2) argument 3598 Add32(Register dst, Register src1, Register src2) argument 3615 AddP(Register dst, Register src1, Register src2) argument 3636 AddP_ExtendSrc(Register dst, Register src1, Register src2) argument 3709 AddLogicalWithCarry32(Register dst, Register src1, Register src2) argument 3726 AddLogical32(Register dst, Register src1, Register src2) argument 3780 SubLogicalWithBorrow32(Register dst, Register src1, Register src2) argument 3798 SubLogical32(Register dst, Register src1, Register src2) argument 3853 Sub32(Register dst, Register src1, Register src2) argument 3873 SubP(Register dst, Register src1, Register src2) argument 3896 SubP_ExtendSrc(Register dst, Register src1, Register src2) argument 3999 And(Register dst, Register src1, Register src2) argument 4016 AndP(Register dst, Register src1, Register src2) argument 4121 Or(Register dst, Register src1, Register src2) argument 4138 OrP(Register dst, Register src1, Register src2) argument 4209 Xor(Register dst, Register src1, Register src2) argument 4226 XorP(Register dst, Register src1, Register src2) argument 4367 Cmp32(Register src1, Register src2) argument 4370 CmpP(Register src1, Register src2) argument 4714 StoreMultipleP(Register src1, Register src2, const MemOperand& mem) argument 4739 StoreMultipleW(Register src1, Register src2, const MemOperand& mem) argument [all...]
H A D	macro-assembler-s390.h	258 void Add32(Register dst, Register src1, Register src2); 259 void AddP(Register dst, Register src1, Register src2); 260 void AddP_ExtendSrc(Register dst, Register src1, Register src2); 272 void AddLogical32(Register dst, Register src1, Register src2); 275 void AddLogicalWithCarry32(Register dst, Register src1, Register src2); 299 void Sub32(Register dst, Register src1, Register src2); 300 void SubP(Register dst, Register src1, Register src2); 301 void SubP_ExtendSrc(Register dst, Register src1, Register src2); 313 void SubLogical32(Register dst, Register src1, Register src2); 315 void SubLogicalWithBorrow32(Register dst, Register src1, Register src2); 594 Push(Register src1, Register src2) argument 601 Push(Register src1, Register src2, Register src3) argument 609 Push(Register src1, Register src2, Register src3, Register src4) argument 618 Push(Register src1, Register src2, Register src3, Register src4, Register src5) argument 642 Pop(Register src1, Register src2) argument 649 Pop(Register src1, Register src2, Register src3) argument 657 Pop(Register src1, Register src2, Register src3, Register src4) argument 666 Pop(Register src1, Register src2, Register src3, Register src4, Register src5) argument [all...]
/external/v8/src/x64/
H A D	assembler-x64.cc	3958 XMMRegister src2) { 3961 emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW1); 3963 emit_sse_operand(dst, src2); 3968 const Operand& src2) { 3971 emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW1); 3973 emit_sse_operand(dst, src2); 3978 XMMRegister src2) { 3981 emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW0); 3983 emit_sse_operand(dst, src2); 3988 const Operand& src2) { 3957 vfmasd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) argument 3967 vfmasd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2) argument 3977 vfmass(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) argument 3987 vfmass(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2) argument 4054 vinstr(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2, SIMDPrefix pp, LeadingOpcode m, VexW w) argument 4064 vinstr(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2, SIMDPrefix pp, LeadingOpcode m, VexW w) argument 4075 vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) argument 4085 vps(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2) argument 4095 vpd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) argument 4105 vpd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2) argument 4133 vss(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) argument 4143 vss(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2) argument [all...]
H A D	macro-assembler-x64.cc	1390 void MacroAssembler::SmiOrIfSmis(Register dst, Register src1, Register src2, 1393 if (dst.is(src1) || dst.is(src2)) { 1395 DCHECK(!src2.is(kScratchRegister)); 1397 orp(kScratchRegister, src2); 1402 orp(dst, src2); 1600 Register src2, 1603 Condition both_smi = CheckBothSmi(src1, src2); 1609 Register src2, 1612 Condition both_smi = CheckBothNonNegativeSmi(src1, src2); 1786 T src2, 1783 SmiAddHelper(MacroAssembler* masm, Register dst, Register src1, T src2, Label* on_not_smi_result, Label::Distance near_jump) argument 1805 SmiAdd(Register dst, Register src1, Register src2, Label* on_not_smi_result, Label::Distance near_jump) argument 1816 SmiAdd(Register dst, Register src1, const Operand& src2, Label* on_not_smi_result, Label::Distance near_jump) argument 1827 SmiAdd(Register dst, Register src1, Register src2) argument 1847 SmiSubHelper(MacroAssembler* masm, Register dst, Register src1, T src2, Label* on_not_smi_result, Label::Distance near_jump) argument 1869 SmiSub(Register dst, Register src1, Register src2, Label* on_not_smi_result, Label::Distance near_jump) argument 1880 SmiSub(Register dst, Register src1, const Operand& src2, Label* on_not_smi_result, Label::Distance near_jump) argument 1892 SmiSubNoOverflowHelper(MacroAssembler* masm, Register dst, Register src1, T src2) argument 1906 SmiSub(Register dst, Register src1, Register src2) argument 1912 SmiSub(Register dst, Register src1, const Operand& src2) argument 1919 SmiMul(Register dst, Register src1, Register src2, Label* on_not_smi_result, Label::Distance near_jump) argument 1974 SmiDiv(Register dst, Register src1, Register src2, Label* on_not_smi_result, Label::Distance near_jump) argument 2037 SmiMod(Register dst, Register src1, Register src2, Label* on_not_smi_result, Label::Distance near_jump) argument 2113 SmiAnd(Register dst, Register src1, Register src2) argument 2136 SmiOr(Register dst, Register src1, Register src2) argument 2157 SmiXor(Register dst, Register src1, Register src2) argument 2246 SmiShiftLeft(Register dst, Register src1, Register src2, Label* on_not_smi_result, Label::Distance near_jump) argument 2297 SmiShiftLogicalRight(Register dst, Register src1, Register src2, Label* on_not_smi_result, Label::Distance near_jump) argument 2334 SmiShiftArithmeticRight(Register dst, Register src1, Register src2) argument 2352 SelectNonSmi(Register dst, Register src1, Register src2, Label* on_not_smis, Label::Distance near_jump) argument 2950 Ucomiss(XMMRegister src1, XMMRegister src2) argument 2960 Ucomiss(XMMRegister src1, const Operand& src2) argument 2970 Ucomisd(XMMRegister src1, XMMRegister src2) argument 2980 Ucomisd(XMMRegister src1, const Operand& src2) argument [all...]
/external/valgrind/VEX/priv/
H A D	guest_amd64_toIR.c	19268 IRTemp src2 = newTemp(Ity_F32); local 19284 assign( src2, 19301 assign( src2, loadLE(Ity_F32, 19320 assign(res2, binop(Iop_RoundF32toInt, mkexpr(rm), mkexpr(src2)) ); 29807 IRTemp src2 = newTemp(ty); local 29951 IRTemp src2 = newTemp(ty); local 30089 IRTemp src2 = newTemp(ty); local 30146 IRTemp src2 = newTemp(ty); local 30273 UInt src2 = getUChar(delta + 1) >> 4; local [all...]
H A D	guest_ppc_toIR.c	1669 static IRTemp gen_vpopcntd_mode32 ( IRTemp src1, IRTemp src2 ) 1703 old = src2; 4439 static IRExpr * CmpGT128U ( IRExpr *src1, IRExpr *src2 ) 4445 unop( Iop_V128HIto64, src2 ), 4449 unop( Iop_V128HIto64, src2 ) ); 4451 unop( Iop_V128to64, src2), 17329 static IRExpr * _get_maxmin_fp_cmp(IRTemp src1, IRTemp src2, Bool isMin) argument 17335 mkexpr( src2 ) ) ) ); 17342 /* else: use src2 */ 17343 mkexpr( src2 ) ); [all...]
H A D	guest_s390_toIR.c	7221 IRTemp src2 = newTemp(Ity_F32); local 7304 assign(src2, get_fpr_w0(4)); /* get source from FPR 4,6 */ 7305 assign(dst2, binop(Iop_F32toD64, irrm, mkexpr(src2))); 7308 s390_cc_thunk_putFZ(S390_CC_OP_PFPO_32, src2, gr0);
H A D	host_amd64_isel.c	1241 HReg src2 = iselIntExpr_R(env, e->Iex.Binop.arg2); local 1243 addInstr(env, AMD64Instr_Alu32R(Aalu_CMP, AMD64RMI_Reg(src2), dst)); 1244 addInstr(env, AMD64Instr_CMov64(Acc_B, src2, dst));
H A D	host_mips_defs.c	1083 MIPSInstr *MIPSInstr_FpTernary ( MIPSFpOp op, HReg dst, HReg src1, HReg src2, argument 1091 i->Min.FpTernary.src2 = src2; 1453 ppHRegMIPS(i->Min.FpTernary.src2, mode64); 1746 addHRegUse(u, HRmRead, i->Min.FpTernary.src2); 1900 mapReg(m, &i->Min.FpTernary.src2); 3514 UInt fr_src2 = fregNo(i->Min.FpTernary.src2, mode64); 3522 UInt fr_src2 = dregNo(i->Min.FpTernary.src2); 3530 UInt fr_src2 = fregNo(i->Min.FpTernary.src2, mode64); 3538 UInt fr_src2 = dregNo(i->Min.FpTernary.src2); [all...]
H A D	host_mips_defs.h	551 HReg src2; member in struct:__anon23995::__anon23996::__anon24019 652 HReg src2, HReg src3 );

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Indexes created Tue Jun 19 19:05:46 CEST 2018