Searched defs:width0 (Results 1 - 19 of 19) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/r200/
H A Dradeon_mipmap_tree.h74 GLuint width0; /** Width of baseLevel image */ member in struct:_radeon_mipmap_tree
105 GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits);
H A Dradeon_mipmap_tree.c160 mt->levels[level].width = minify(mt->width0, i);
180 GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits)
194 mt->width0 = width0;
329 fprintf(stderr, "width0 %d vs %d\n", mtBaseLevel->width, firstImage->Width);
178 radeon_miptree_create(radeonContextPtr rmesa, GLenum target, mesa_format mesaFormat, GLuint baseLevel, GLuint numLevels, GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits) argument
/external/mesa3d/src/mesa/drivers/dri/radeon/
H A Dradeon_mipmap_tree.h74 GLuint width0; /** Width of baseLevel image */ member in struct:_radeon_mipmap_tree
105 GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits);
H A Dradeon_mipmap_tree.c160 mt->levels[level].width = minify(mt->width0, i);
180 GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits)
194 mt->width0 = width0;
329 fprintf(stderr, "width0 %d vs %d\n", mtBaseLevel->width, firstImage->Width);
178 radeon_miptree_create(radeonContextPtr rmesa, GLenum target, mesa_format mesaFormat, GLuint baseLevel, GLuint numLevels, GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits) argument
/external/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_state_sampler.c263 unsigned width0 = tex->width0; local
311 width0 = view->u.buf.size / view_blocksize;
313 assert(view->u.buf.offset + view->u.buf.size <= res->width0);
333 width0, tex->height0, num_layers,
/external/mesa3d/src/gallium/drivers/i915/
H A Di915_surface.c46 unsigned width0,
85 unsigned src_width0 = src->width0;
87 unsigned dst_width0 = dst->width0;
357 unsigned width0,
373 ps->width = u_minify(width0, surf_tmpl->u.tex.level);
389 pt->width0, pt->height0);
354 i915_create_surface_custom(struct pipe_context *ctx, struct pipe_resource *pt, const struct pipe_surface *surf_tmpl, unsigned width0, unsigned height0) argument
H A Di915_state.c433 tex->width0, tex->height0, tex->depth0,
703 new_num = ibuf->b.b.width0 / 4 * sizeof(float);
712 diff = memcmp(old->data, ibuf->data, ibuf->b.b.width0);
819 unsigned width0,
816 i915_create_sampler_view_custom(struct pipe_context *pipe, struct pipe_resource *texture, const struct pipe_sampler_view *templ, unsigned width0, unsigned height0) argument
/external/mesa3d/src/gallium/drivers/softpipe/
H A Dsp_state_sampler.c190 unsigned width0 = tex->width0; local
243 width0 = view->u.buf.size / view_blocksize;
245 assert(view->u.buf.offset + view->u.buf.size <= res->width0);
265 width0, tex->height0, num_layers,
/external/mesa3d/src/mesa/state_tracker/
H A Dst_texture.c51 * width0, height0, depth0 are the dimensions of the level 0 image
60 GLuint width0,
71 assert(width0 > 0);
88 pt.width0 = width0;
224 if (ptWidth != u_minify(pt->width0, image->Level) ||
327 region.x = src->width0 / 2;
354 GLuint width = u_minify(dst->width0, dstLevel);
360 if (u_minify(src->width0, srcLevel) != width ||
56 st_texture_create(struct st_context *st, enum pipe_texture_target target, enum pipe_format format, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, GLuint layers, GLuint nr_samples, GLuint bind ) argument
H A Dst_cb_texture.c371 GLuint *width0, GLuint *height0, GLuint *depth0)
425 *width0 = width;
1504 &src_templ.width0, &src_templ.height0,
1509 (!util_is_power_of_two(src_templ.width0) ||
1972 &dst_templ.width0, &dst_templ.height0,
2411 assert(u_minify(stImage->pt->width0, src_level) == stImage->base.Width);
2520 u_minify(stObj->pt->width0, firstImage->base.Level) == width &&
2523 ptWidth = stObj->pt->width0;
2557 stObj->pt->width0 != ptWidth ||
2744 &pt.width0,
369 guess_base_level_size(GLenum target, GLuint width, GLuint height, GLuint depth, GLuint level, GLuint *width0, GLuint *height0, GLuint *depth0) argument
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/external/mesa3d/src/gallium/drivers/ilo/core/
H A Dilo_image.h146 unsigned width0; member in struct:ilo_image
/external/mesa3d/src/mesa/drivers/dri/i915/
H A Dintel_mipmap_tree.c69 GLuint width0,
86 mt->logical_width0 = width0;
106 mt->physical_width0 = width0;
128 uint32_t width0,
166 GLuint width0,
177 first_level, last_level, width0,
190 uint32_t tiling = intel_miptree_choose_tiling(intel, format, width0,
64 intel_miptree_create_layout(struct intel_context *intel, GLenum target, mesa_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0) argument
126 intel_miptree_choose_tiling(struct intel_context *intel, mesa_format format, uint32_t width0, enum intel_miptree_tiling_mode requested, struct intel_mipmap_tree *mt) argument
161 intel_miptree_create(struct intel_context *intel, GLenum target, mesa_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, bool expect_accelerated_upload, enum intel_miptree_tiling_mode requested_tiling) argument
/external/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_blit.c827 unsigned width0; member in struct:texture_orig_info
864 dst_width = u_minify(dst->width0, dst_level);
866 src_width0 = src->width0;
978 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
1007 dst_width == info->src.resource->width0 &&
1063 templ.width0 = info->src.resource->width0;
H A Dsi_state.c2768 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3021 * @param width0 width0 override (for compressed textures as int)
3029 unsigned width0, unsigned height0,
3079 width = width0;
3174 texture ? texture->width0 : 0,
3724 res->width0, res->height0, res->depth0,
3026 si_create_sampler_view_custom(struct pipe_context *ctx, struct pipe_resource *texture, const struct pipe_sampler_view *state, unsigned width0, unsigned height0, unsigned force_level) argument
/external/mesa3d/src/gallium/drivers/r300/
H A Dr300_context.h330 * Most of the time, these are equal to pipe_texture::width0, height0,
334 unsigned width0, height0, depth0; member in struct:r300_texture_desc
/external/mesa3d/src/gallium/drivers/r600/
H A Dr600_state.c624 unsigned width0, unsigned height0)
686 return texture_buffer_sampler_view(view, texture->width0, 1);
787 u_minify(tex->width0, state->u.tex.first_level),
975 rctx->dummy_cmask->b.b.width0 < cmask.size ||
995 rctx->dummy_fmask->b.b.width0 < fmask.size ||
1658 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1707 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
2951 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
2952 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
623 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view, unsigned width0, unsigned height0) argument
H A Devergreen_state.c602 unsigned width0, unsigned height0)
659 unsigned width0, unsigned height0,
690 return texture_buffer_sampler_view(rctx, view, width0, height0);
741 width = width0;
879 tex->width0, tex->height0, 0);
952 unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
977 surf->cb_color_dim = pipe_buffer->width0;
981 0, pipe_buffer->width0);
1814 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1884 radeon_emit(cs, rbuffer->b.b.width0
600 texture_buffer_sampler_view(struct r600_context *rctx, struct r600_pipe_sampler_view *view, unsigned width0, unsigned height0) argument
656 evergreen_create_sampler_view_custom(struct pipe_context *ctx, struct pipe_resource *texture, const struct pipe_sampler_view *state, unsigned width0, unsigned height0, unsigned force_level) argument
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/external/mesa3d/src/gallium/include/pipe/
H A Dp_state.h495 unsigned width0; member in struct:pipe_resource
580 * 'buffer->width0 - buffer_offset', so buffer_size refers to the size
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dintel_mipmap_tree.c300 GLuint width0,
322 mt->logical_width0 = width0;
400 width0 = ALIGN(width0, 2) * 2;
404 width0 = ALIGN(width0, 2) * 2;
408 width0 = ALIGN(width0, 2) * 4;
412 width0 = ALIGN(width0,
295 intel_miptree_create_layout(struct brw_context *brw, GLenum target, mesa_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, GLuint num_samples, uint32_t layout_flags) argument
606 miptree_create(struct brw_context *brw, GLenum target, mesa_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, GLuint num_samples, uint32_t layout_flags) argument
677 intel_miptree_create(struct brw_context *brw, GLenum target, mesa_format format, GLuint first_level, GLuint last_level, GLuint width0, GLuint height0, GLuint depth0, GLuint num_samples, uint32_t layout_flags) argument
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