/external/ltp/testcases/kernel/security/mmc_security/ |
H A D | ask_password.sh | 29 #* - non zero on failure. return value from commands ($RC) *# 47 RC=0 # Exit values of system commands used 65 ask_password || exit $RC
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H A D | assign_password.sh | 45 RC=0 # Exit values of system commands used 70 assign_password || exit $RC
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H A D | remove_password.sh | 45 RC=0 # Exit values of system commands used 64 remove_password || exit $RC
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H A D | change_password.sh | 43 RC=0 # Exit values of system commands used 80 change_password || exit $RC
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H A D | force_erase.sh | 46 RC=0 # Exit values of system commands used 75 force_erase || exit $RC
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/external/ltp/testcases/kernel/power_management/ |
H A D | runpwtests05.sh | 55 RC=0 58 analyze_sched_domain_result $sched_mc $ret; RC=$? 60 if [ $RC -eq 0 ]; then 67 RC=0 72 analyze_sched_domain_result $sched_mc $ret $sched_smt; RC=$? 75 if [ $RC -eq 0 ]; then
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H A D | runpwtests_exclusive01.sh | 50 RC=0 65 $sched_mc_pass_cnt; RC=$? 67 if [ $RC -eq 0 ]; then 73 RC=0 91 $sched_mc_smt_pass_cnt $sched_smt; RC=$? 94 if [ $RC -eq 0 ]; then
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H A D | runpwtests_exclusive05.sh | 50 RC=0 63 RC=1 68 if [ $RC -eq 0 ]; then 74 RC=0 87 RC=1 94 if [ $RC -eq 0 ]; then
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H A D | runpwtests_exclusive02.sh | 48 RC=0 64 $sched_smt_pass_cnt; RC=$? 66 if [ $RC -eq 0 ]; then
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H A D | pm_include.sh | 104 RC=0 113 RC=1 118 RC=1 122 return $RC 177 RC=0 186 RC=1 193 RC=1 204 RC=1 213 return $RC 230 RC [all...] |
/external/linux-kselftest/tools/testing/selftests/powerpc/include/ |
H A D | instructions.h | 32 #define __PASTE(RA, RB, L, RC) \ 33 (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31)) 34 #define PASTE(RA, RB, L, RC) \ 35 .long __PASTE((RA), (RB), (L), (RC))
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/external/ltp/testcases/kernel/syscalls/ioctl/ |
H A D | test_ioctl | 49 RC=$? 50 if [ $RC -eq 0 ] 72 RC=$? 73 if [ $RC -eq 0 ]
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/external/llvm/lib/CodeGen/GlobalISel/ |
H A D | RegisterBank.cpp | 29 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); local 31 if (!covers(RC)) 37 // RegisterBankInfo to find the subclasses of RC, to make sure 42 if (!RC.hasSubClassEq(&SubRC)) 55 bool RegisterBank::covers(const TargetRegisterClass &RC) const { 57 return ContainedRegClasses.test(RC.getID()); 97 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); local 99 if (!covers(RC)) 104 OS << TRI->getRegClassName(&RC);
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/external/llvm/lib/CodeGen/ |
H A D | LiveStackAnalysis.cpp | 58 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument 66 S2RCMap.insert(std::make_pair(Slot, RC)); 70 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); 82 const TargetRegisterClass *RC = getIntervalRegClass(Slot); local 83 if (RC) 84 OS << " [" << TRI->getRegClassName(RC) << "]\n";
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H A D | RegisterClassInfo.cpp | 76 /// compute - Compute the preferred allocation order for RC with reserved 79 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { 80 assert(RC && "no register class given"); 81 RCInfo &RCI = RegClass[RC->getID()]; 84 unsigned NumRegs = RC->getNumRegs(); 97 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF); 133 // Check if RC is a proper sub-class. 135 TRI->getLargestLegalSuperClass(RC, *MF)) 136 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) 143 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") 157 const TargetRegisterClass *RC = nullptr; local [all...] |
H A D | TargetRegisterInfo.cpp | 111 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { 112 if (!RC || RC->isAllocatable()) 113 return RC; 115 for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid(); 135 const TargetRegisterClass* RC = *I; 136 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) && 137 (!BestRC || BestRC->hasSubClass(RC))) 138 BestRC = RC; [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | LiveStackAnalysis.cpp | 55 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument 61 S2RCMap.insert(std::make_pair(Slot, RC)); 65 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); 77 const TargetRegisterClass *RC = getIntervalRegClass(Slot); local 78 if (RC) 79 OS << " [" << RC->getName() << "]\n";
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitTracker.cpp | 82 const TargetRegisterClass *RC = MRI.getRegClass(Reg); local 83 unsigned ID = RC->getID(); 205 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW) 207 assert(RW <= RC.width()); 208 return eXTR(RC, 0, RW); 211 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) 213 uint16_t W = RC.width(); 215 return eXTR(RC, W-RW, W); 218 auto half = [this] (const BT::RegisterCell &RC, unsigned N) 220 assert(N*16+16 <= RC [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ |
H A D | TargetRegisterInfo.cpp | 62 const TargetRegisterClass* RC = *I; local 63 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) && 64 (!BestRC || BestRC->hasSubClass(RC))) 65 BestRC = RC; 75 const TargetRegisterClass *RC, BitVector &R){ 76 ArrayRef<unsigned> Order = RC->getRawAllocationOrder(MF); 82 const TargetRegisterClass *RC) const { 84 if (RC) { 85 getAllocatableSetForRC(MF, RC, Allocatabl 74 getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R) argument [all...] |
/external/ltp/ |
H A D | ltpmenu | 110 you wish to continue ??" 7 70 || RC=$? 111 case $RC in 164 RC=0 168 while [ $RC -ne "1" ] 175 2>/tmp/runltp.results.$$ || RC=$? 223 RC=$? 224 if [ $RC -eq "0" ] 241 RC=$? 242 if [ $RC -eq "0" ] 282 RC [all...] |
/external/swiftshader/third_party/LLVM/utils/release/ |
H A D | test-release.sh | 28 RC="" 61 -rc | --rc | -RC | --RC ) 63 RC=$1 115 if [ -z "$RC" ]; then 135 BuildDir=$BuildDir/rc$RC 152 if ! svn ls $Base_url/$proj/tags/RELEASE_$Release_no_dot/rc$RC > /dev/null 2>&1 ; then 153 echo "llvm $Release release candidate $RC doesn't exist!" 164 echo "# Exporting $proj $Release-RC$RC source [all...] |
/external/ltp/testscripts/ |
H A D | tpm_tools.sh | 53 RC=0 69 RC=1 82 RC=1 90 RC=1 103 RC=1 110 RC=1 124 RC=1 132 RC=1 144 RC=1 154 if [ $RC [all...] |
/external/llvm/lib/Target/AMDGPU/ |
H A D | SIRegisterInfo.h | 93 bool isSGPRClass(const TargetRegisterClass *RC) const { 94 return !hasVGPRs(RC); 103 const TargetRegisterClass *RC; local 105 RC = MRI.getRegClass(Reg); 107 RC = getPhysRegClass(Reg); 108 return isSGPRClass(RC); 112 bool hasVGPRs(const TargetRegisterClass *RC) const; 117 static bool isPseudoRegClass(const TargetRegisterClass *RC) { argument 118 return RC == &AMDGPU::VS_32RegClass || RC [all...] |
/external/llvm/unittests/Analysis/ |
H A D | LazyCallGraphTest.cpp | 347 LazyCallGraph::RefSCC &RC = *I++; local 351 auto J = RC.begin(); 392 EXPECT_EQ(RC.end(), J); 431 LazyCallGraph::RefSCC &RC = *I++; local 439 EXPECT_EQ(&RC, CG.lookupRefSCC(N1)); 440 EXPECT_EQ(&RC, CG.lookupRefSCC(N2)); 441 EXPECT_EQ(&RC, CG.lookupRefSCC(N3)); 442 EXPECT_EQ(&RC, CG.lookupRefSCC(N4)); 443 EXPECT_EQ(&RC, CG.lookupRefSCC(N5)); 445 ASSERT_EQ(1, RC 771 LazyCallGraph::RefSCC &RC = *I++; local 859 LazyCallGraph::RefSCC &RC = *I++; local 917 LazyCallGraph::RefSCC &RC = *I++; local 1004 LazyCallGraph::RefSCC &RC = *I++; local 1116 LazyCallGraph::RefSCC &RC = *I++; local 1246 LazyCallGraph::RefSCC &RC = *I++; local [all...] |
/external/swiftshader/third_party/LLVM/include/llvm/Target/ |
H A D | TargetRegisterInfo.h | 142 bool hasSubClass(const TargetRegisterClass *RC) const { 143 return RC != this && hasSubClassEq(RC); 146 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this 148 bool hasSubClassEq(const TargetRegisterClass *RC) const { 149 unsigned ID = RC->getID(); 155 bool hasSuperClass(const TargetRegisterClass *RC) const { 156 return RC->hasSubClass(this); 159 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this 161 bool hasSuperClassEq(const TargetRegisterClass *RC) cons 396 canCombineSubRegIndices(const TargetRegisterClass *RC, SmallVectorImpl<unsigned> &SubIndices, unsigned &NewSubIdx) const argument 648 saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const argument [all...] |