Searched refs:MVT (Results 251 - 261 of 261) sorted by relevance

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/external/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp569 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
1189 SequenceToOffsetTable<SmallVector<MVT::SimpleValueType, 4> > VTSeqs;
1193 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
1194 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
H A DCodeGenRegisters.cpp708 SpillSize = Size ? Size : MVT(VTs[0]).getSizeInBits();
/external/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp612 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other);
H A DMachineScheduler.cpp2576 for (unsigned VT = MVT::i32; VT > (unsigned)MVT::i1; --VT) {
2577 MVT::SimpleValueType LegalIntVT = (MVT::SimpleValueType)VT;
H A DCodeGenPrepare.cpp3160 auto PtrTy = MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
4779 MVT RegType = TLI->getRegisterType(Context, TLI->getValueType(*DL, OldType));
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp621 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other);
H A DMachineLICM.cpp673 if (VT == MVT::untyped) {
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp6536 VT, MVT::Other, AddrOps);
6552 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
6582 dl, MVT::Other, AddrOps);
6749 case MVT::i8:
6750 case MVT::i16:
6751 case MVT::i32:
6752 case MVT::i64:
6753 case MVT::f32:
6754 case MVT::f64:
/external/llvm/lib/Target/AMDGPU/
H A DAMDILCFGStructurizer.cpp1270 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32);
H A DSIInstrInfo.cpp40 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
47 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
/external/llvm/lib/Target/NVPTX/
H A DNVPTXAsmPrinter.cpp1453 MVT thePointerTy = TLI->getPointerTy(DL);

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