Searched refs:MVT (Results 251 - 261 of 261) sorted by relevance
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/external/llvm/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 569 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { 1189 SequenceToOffsetTable<SmallVector<MVT::SimpleValueType, 4> > VTSeqs; 1193 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; 1194 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
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H A D | CodeGenRegisters.cpp | 708 SpillSize = Size ? Size : MVT(VTs[0]).getSizeInBits();
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/external/llvm/lib/CodeGen/ |
H A D | AggressiveAntiDepBreaker.cpp | 612 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other);
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H A D | MachineScheduler.cpp | 2576 for (unsigned VT = MVT::i32; VT > (unsigned)MVT::i1; --VT) { 2577 MVT::SimpleValueType LegalIntVT = (MVT::SimpleValueType)VT;
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H A D | CodeGenPrepare.cpp | 3160 auto PtrTy = MVT::getIntegerVT(DL.getPointerSizeInBits(AS)); 4779 MVT RegType = TLI->getRegisterType(Context, TLI->getValueType(*DL, OldType));
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | AggressiveAntiDepBreaker.cpp | 621 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other);
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H A D | MachineLICM.cpp | 673 if (VT == MVT::untyped) {
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 6536 VT, MVT::Other, AddrOps); 6552 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs()) 6582 dl, MVT::Other, AddrOps); 6749 case MVT::i8: 6750 case MVT::i16: 6751 case MVT::i32: 6752 case MVT::i64: 6753 case MVT::f32: 6754 case MVT::f64:
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/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDILCFGStructurizer.cpp | 1270 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32);
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H A D | SIInstrInfo.cpp | 40 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue) 47 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXAsmPrinter.cpp | 1453 MVT thePointerTy = TLI->getPointerTy(DL);
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Completed in 335 milliseconds
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