/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyFastISel.cpp | 582 const TargetRegisterClass *RC; local 589 RC = &WebAssembly::I32RegClass; 593 RC = &WebAssembly::I64RegClass; 597 RC = &WebAssembly::F32RegClass; 601 RC = &WebAssembly::F64RegClass; 606 unsigned ResultReg = createResultReg(RC); 736 const TargetRegisterClass *RC; local 743 RC = &WebAssembly::I32RegClass; 747 RC = &WebAssembly::I64RegClass; 751 RC 983 const TargetRegisterClass *RC; local 1036 const TargetRegisterClass *RC; local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 702 const TargetRegisterClass *RC = local 704 if (!RC) 708 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && 709 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && 710 !PPC::G8RCRegClass.hasSubClassEq(RC) && 711 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) 738 const TargetRegisterClass *RC = local 740 assert(RC && "TrueReg and FalseReg must have overlapping register classes"); 742 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) || 743 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC); 956 StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs, bool &NonRI, bool &SpillsVRS) const argument 1058 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 1091 LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr *> &NewMIs, bool &NonRI, bool &SpillsVRS) const argument 1167 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
H A D | PPCVSXCopy.cpp | 56 bool IsRegInClass(unsigned Reg, const TargetRegisterClass *RC, argument 59 return RC->hasSubClassEq(MRI.getRegClass(Reg)); 60 } else if (RC->contains(Reg)) {
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/external/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 130 const TargetRegisterClass *RC); 358 const TargetRegisterClass *RC = nullptr; local 364 RC = &X86::GR8RegClass; 368 RC = &X86::GR16RegClass; 372 RC = &X86::GR32RegClass; 377 RC = &X86::GR64RegClass; 382 RC = &X86::FR32RegClass; 385 RC = &X86::RFP32RegClass; 391 RC = &X86::FR64RegClass; 394 RC 757 const TargetRegisterClass *RC = nullptr; local 1703 const TargetRegisterClass *RC = nullptr; local 1787 const TargetRegisterClass *RC; member in struct:DivRemEntry 1946 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local 2122 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local 2216 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local 2244 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local 2285 const TargetRegisterClass *RC = nullptr; local 2309 X86SelectFPExtOrFPTrunc(const Instruction *I, unsigned TargetOpc, const TargetRegisterClass *RC) argument 2462 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::v8i16); local 2517 const TargetRegisterClass *RC = nullptr; local 2659 const TargetRegisterClass *RC; local 2965 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); local 3546 const TargetRegisterClass *RC = nullptr; local 3686 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy(DL)); local 3700 const TargetRegisterClass *RC = nullptr; local [all...] |
H A D | X86FixupSetCC.cpp | 160 const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit() local 163 unsigned ZeroReg = MRI->createVirtualRegister(RC); 164 unsigned InsertReg = MRI->createVirtualRegister(RC);
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/external/llvm/lib/Target/AMDGPU/ |
H A D | SIInsertWaits.cpp | 106 RegInterval getRegInterval(const TargetRegisterClass *RC, 204 const TargetRegisterClass *RC = TII->getOpRegClass(MI, 0); local 205 unsigned Size = RC->getSize(); 275 RegInterval SIInsertWaits::getRegInterval(const TargetRegisterClass *RC, argument 277 unsigned Size = RC->getSize(); 341 const TargetRegisterClass *RC = TII->getOpRegClass(*I, i); local 342 RegInterval Interval = getRegInterval(RC, Op); 471 const TargetRegisterClass *RC = TII->getOpRegClass(MI, i); local 472 RegInterval Interval = getRegInterval(RC, Op);
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H A D | SIRegisterInfo.cpp | 708 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const { 709 switch (RC->getSize()) { 713 return getCommonSubClass(&AMDGPU::VGPR_32RegClass, RC) != nullptr; 715 return getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) != nullptr; 717 return getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) != nullptr; 719 return getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) != nullptr; 721 return getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) != nullptr; 723 return getCommonSubClass(&AMDGPU::VReg_512RegClass, RC) != nullptr; 768 const TargetRegisterClass *RC, unsigned SubIdx) const { 770 return RC; 767 getSubRegClass( const TargetRegisterClass *RC, unsigned SubIdx) const argument 880 const TargetRegisterClass *RC = getPhysRegClass(Reg); local 1007 const TargetRegisterClass *RC; local [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | TargetInstrInfoImpl.cpp | 248 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg); local 251 return RC->contains(LiveOp.getReg()) ? RC : 0; 253 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg))) 254 return RC; 313 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]); local 314 if (!RC) 322 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI); 324 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
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H A D | VirtRegMap.cpp | 103 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) { argument 104 int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(), 105 RC->getAlignment()); 133 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); local 134 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC); 162 int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) { argument 164 EmergencySpillSlots.find(RC); 167 return EmergencySpillSlots[RC] = createSpillSlot(RC);
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/external/autotest/client/site_tests/firmware_TouchMTB/ |
H A D | firmware_constants.py | 208 RC = _RobotControl() variable 209 RC.PAUSE_TYPE = 'pause_type' 210 RC.PROMPT = 'finger_control_prompt' 214 RC.PER_GESTURE = 'per_gesture' 218 RC.PER_VARIATION = 'per_variation'
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/external/ltp/testcases/commands/mail/ |
H A D | mail_tests.sh | 61 RC=0 96 # Set return code RC variable to 0, it will be set with a non-zero return code 100 RC=0 229 RC=0 299 RC=0 335 RC=0
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 334 const TargetRegisterClass *RC, 337 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) { 353 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) { 369 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) { 374 } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) { 379 } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) { 417 } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) { 451 } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) { 474 const TargetRegisterClass *RC, 479 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMI 331 StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 471 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 498 LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 596 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.cpp | 1091 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); local 1092 HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI); 1144 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); local 1146 HII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, &HRI); 1205 /// Returns true if there are no caller-saved registers available in class RC. 1207 const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) { 1219 for (const MCPhysReg *P = HRI.getCallerSavedRegs(&MF, RC); *P; ++P) 1323 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg); local 1324 int FI = MFI->CreateFixedSpillStackObject(RC->getSize(), S->Offset); 1335 const TargetRegisterClass *RC local 1206 needToReserveScavengingSpillSlots(MachineFunction &MF, const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) argument 1473 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass local 1513 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass local 1558 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass local 1611 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass local 1660 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass local 1697 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass local 1876 const TargetRegisterClass *RC; member in struct:SlotInfo 1950 const TargetRegisterClass *RC = nullptr; local 2112 auto *RC = getRegClass({SrcOp.getReg(), SrcOp.getSubReg()}); local [all...] |
/external/clang/test/Layout/ |
H A D | ms-x86-pack-and-align.cpp | 434 struct RC { struct 440 RC c; 472 // CHECK-NEXT: 0 | struct RC 480 // CHECK-NEXT: 1 | struct RC c 513 // CHECK-X64-NEXT: 0 | struct RC 521 // CHECK-X64-NEXT: 1 | struct RC c 798 sizeof(RC)+
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/external/llvm/lib/CodeGen/GlobalISel/ |
H A D | RegisterBankInfo.cpp | 178 const TargetRegisterClass *RC = local 180 if (RC) 181 return &getRegBankFromRegClass(*RC); 190 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI); local 192 if (!RC) 195 const RegisterBank &RegBank = getRegBankFromRegClass(*RC); 197 assert(RegBank.covers(*RC) && 365 const TargetRegisterClass *RC = nullptr; local 370 RC = TRI.getMinimalPhysRegClass(Reg); 378 RC [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.h | 125 getCrossCopyRegClass(const TargetRegisterClass *RC) const override; 128 getLargestLegalSuperClass(const TargetRegisterClass *RC, 131 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
H A D | BlackfinFrameLowering.cpp | 122 const TargetRegisterClass *RC = BF::DPRegisterClass; local 126 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 127 RC->getAlignment(),
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
H A D | MipsInstrInfo.cpp | 168 const TargetRegisterClass *RC, 174 if (RC == Mips::CPURegsRegisterClass) 176 else if (RC == Mips::CPU64RegsRegisterClass) 178 else if (RC == Mips::FGR32RegisterClass) 180 else if (RC == Mips::AFGR64RegisterClass) 182 else if (RC == Mips::FGR64RegisterClass) 193 const TargetRegisterClass *RC, 200 if (RC == Mips::CPURegsRegisterClass) 202 else if (RC == Mips::CPU64RegsRegisterClass) 204 else if (RC 166 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 191 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.cpp | 40 const TargetRegisterClass *RC, 52 if (RC == &MSP430::GR16RegClass) 56 else if (RC == &MSP430::GR8RegClass) 67 const TargetRegisterClass *RC, 79 if (RC == &MSP430::GR16RegClass) 83 else if (RC == &MSP430::GR8RegClass) 37 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 64 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.cpp | 38 const TargetRegisterClass *RC, 52 if (RC == &MSP430::GR16RegClass) 56 else if (RC == &MSP430::GR8RegClass) 67 const TargetRegisterClass *RC, 81 if (RC == &MSP430::GR16RegClass) 84 else if (RC == &MSP430::GR8RegClass) 35 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 64 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/CodeGen/ |
H A D | MachineRegisterInfo.cpp | 39 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument 40 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); 41 VRegInfo[Reg].first = RC; 51 const TargetRegisterClass *RC, 54 if (OldRC == RC) 55 return RC; 57 getTargetRegisterInfo()->getCommonSubClass(OldRC, RC); 50 constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) argument
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/external/llvm/lib/MC/ |
H A D | MCRegisterInfo.cpp | 19 const MCRegisterClass *RC) const { 21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16InstrInfo.h | 53 const TargetRegisterClass *RC, 60 const TargetRegisterClass *RC,
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H A D | MipsSEISelLowering.h | 28 void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC); 32 const TargetRegisterClass *RC);
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/external/ltp/testcases/commands/cron/ |
H A D | cron_pos_tests.sh | 27 RC=$? 29 exit $RC
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