Searched refs:BaseReg (Results 1 - 25 of 92) sorted by relevance

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/external/swiftshader/third_party/LLVM/include/llvm/Transforms/Utils/
H A DAddrModeMatcher.h37 Value *BaseReg; member in struct:llvm::ExtAddrMode
39 ExtAddrMode() : BaseReg(0), ScaledReg(0) {}
44 return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) &&
/external/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.h77 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
79 void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
82 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
H A DAArch64StorePairSuppress.cpp146 unsigned BaseReg; local
148 if (TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI)) {
149 if (PrevBaseReg == BaseReg) {
158 PrevBaseReg = BaseReg;
H A DAArch64RegisterInfo.cpp314 unsigned BaseReg,
322 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
325 unsigned BaseReg,
337 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
340 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
346 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, argument
358 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
313 isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const argument
324 materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const argument
H A DAArch64LoadStoreOptimizer.cpp147 unsigned BaseReg, int Offset);
1104 unsigned BaseReg = getLdStBaseOp(LoadMI).getReg(); local
1128 // it's unnecessary to check if BaseReg is modified by the store itself.
1130 BaseReg == getLdStBaseOp(MI).getReg() &&
1145 if (ModifiedRegs[BaseReg])
1217 unsigned BaseReg = getLdStBaseOp(FirstMI).getReg(); local
1269 if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) ||
1347 if (ModifiedRegs[BaseReg])
1422 unsigned BaseReg, int Offset) {
1441 if (MI.getOperand(0).getReg() != BaseReg ||
1420 isMatchingUpdateInsn(MachineInstr &MemMI, MachineInstr &MI, unsigned BaseReg, int Offset) argument
1480 unsigned BaseReg = getLdStBaseOp(MemMI).getReg(); local
1534 unsigned BaseReg = getLdStBaseOp(MemMI).getReg(); local
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/external/swiftshader/third_party/LLVM/lib/Target/X86/InstPrinter/
H A DX86ATTInstPrinter.cpp110 const MCOperand &BaseReg = MI->getOperand(Op); local
123 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
130 if (IndexReg.getReg() || BaseReg.getReg()) {
132 if (BaseReg.getReg())
H A DX86IntelInstPrinter.cpp97 const MCOperand &BaseReg = MI->getOperand(Op); local
112 if (BaseReg.getReg()) {
132 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
/external/llvm/lib/CodeGen/
H A DLocalStackSlotAllocation.cpp255 lookupCandidateBaseReg(unsigned BaseReg, argument
264 return TRI->isFrameOffsetLegal(&MI, BaseReg, Offset);
326 unsigned BaseReg = 0; local
362 lookupCandidateBaseReg(BaseReg, BaseOffset, FrameSizeAdjust,
364 DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n");
381 BaseReg, BaseOffset, FrameSizeAdjust,
390 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
392 DEBUG(dbgs() << " Materializing base register " << BaseReg <<
398 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx,
409 assert(BaseReg !
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/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DLocalStackSlotAllocation.cpp294 unsigned BaseReg = 0; local
314 BaseReg = RegOffset.first;
322 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
324 DEBUG(dbgs() << " Materializing base register " << BaseReg <<
331 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx,
342 std::pair<unsigned, int64_t>(BaseReg, BaseOffset));
346 assert(BaseReg != 0 && "Unable to allocate virtual base register!");
350 TRI->resolveFrameIndex(I, BaseReg, Offset);
/external/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp125 const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes,
130 (BaseReg != 0 && !isARMLowRegister(BaseReg));
142 assert(BaseReg == ARM::SP && "Unexpected!");
168 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
170 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
181 unsigned BaseReg, int NumBytes,
201 // DestReg and BaseReg are low, high or the stack pointer.
202 // * CopyOpc - DestReg = BaseReg + imm
203 // This will be emitted once if DestReg != BaseReg, an
123 emitThumbRegPlusImmInReg( MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags = MachineInstr::NoFlags) argument
178 emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags) argument
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H A DARMBaseRegisterInfo.h151 unsigned BaseReg, int FrameIdx,
153 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
155 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
H A DThumbRegisterInfo.h53 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
H A DThumb2InstrInfo.cpp224 unsigned BaseReg, int NumBytes,
228 if (NumBytes == 0 && DestReg != BaseReg) {
230 .addReg(BaseReg, RegState::Kill)
240 if (DestReg != ARM::SP && DestReg != BaseReg &&
262 .addReg(BaseReg)
268 // know anything about BaseReg. t2ADDrr is an invalid
271 // do not generate invalid encoding, put BaseReg first.
273 .addReg(BaseReg)
285 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
288 .addReg(BaseReg)
221 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
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/external/swiftshader/third_party/LLVM/lib/Transforms/Utils/
H A DAddrModeMatcher.cpp42 if (BaseReg) {
45 WriteAsOperand(OS, BaseReg, /*PrintType=*/false);
275 AddrMode.BaseReg = AddrInst->getOperand(0);
288 AddrMode.BaseReg = AddrInst->getOperand(0);
356 AddrMode.BaseReg = Addr;
361 AddrMode.BaseReg = 0;
521 // BaseReg and ScaleReg (global addresses are always available, as are any
523 Value *BaseReg = AMAfter.BaseReg, *ScaledReg = AMAfter.ScaledReg;
525 // If the BaseReg o
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DThumb1RegisterInfo.cpp92 unsigned DestReg, unsigned BaseReg,
99 (BaseReg != 0 && !isARMLowRegister(BaseReg));
111 assert(BaseReg == ARM::SP && "Unexpected!");
134 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
136 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
169 unsigned DestReg, unsigned BaseReg,
185 if (DestReg == BaseReg && BaseReg == ARM::SP) {
191 } else if (!isSub && BaseReg
89 emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags = MachineInstr::NoFlags) argument
166 emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags) argument
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H A DThumb2InstrInfo.cpp176 unsigned DestReg, unsigned BaseReg, int NumBytes,
184 if (DestReg != ARM::SP && DestReg != BaseReg &&
206 .addReg(BaseReg, RegState::Kill)
213 .addReg(BaseReg, RegState::Kill)
224 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
227 .addReg(BaseReg).setMIFlags(MIFlags));
228 BaseReg = ARM::SP;
233 if (BaseReg == ARM::SP) {
239 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
257 assert(DestReg != ARM::SP && BaseReg !
174 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
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H A DThumb1RegisterInfo.h58 unsigned BaseReg, int64_t Offset) const;
H A DARMBaseRegisterInfo.h147 unsigned BaseReg, int FrameIdx,
150 unsigned BaseReg, int64_t Offset) const;
/external/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h68 unsigned BaseReg, int FrameIdx,
71 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
74 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
/external/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.h128 unsigned BaseReg, int FrameIdx,
130 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
132 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
/external/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.h70 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
74 bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg,
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
H A DBlackfinRegisterInfo.cpp207 unsigned BaseReg = BF::FP;
211 BaseReg = BF::SP;
223 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
231 if (BaseReg == BF::FP && isUInt<7>(-Offset)) {
258 MI.getOperand(2).ChangeToRegister(BaseReg, false);
272 .addReg(BaseReg);
296 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
308 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
/external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp135 unsigned BaseReg; member in struct:__anon20123::X86Operand::__anon20124::__anon20128
181 return Mem.BaseReg;
344 Res->Mem.BaseReg = 0;
352 unsigned BaseReg, unsigned IndexReg,
356 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
364 Res->Mem.BaseReg = BaseReg;
380 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0);
389 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;
581 unsigned BaseReg local
351 CreateMem(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc, SMLoc EndLoc) argument
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/external/llvm/lib/Target/X86/InstPrinter/
H A DX86ATTInstPrinter.cpp197 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); local
212 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
219 if (IndexReg.getReg() || BaseReg.getReg()) {
221 if (BaseReg.getReg())
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp264 unsigned BaseReg, IndexReg, TmpReg, Scale; member in class:__anon13327::X86AsmParser::IntelExprStateMachine
274 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
278 unsigned getBaseReg() { return BaseReg; }
382 // If we already have a BaseReg, then assume this is the IndexReg with
384 if (!BaseReg) {
385 BaseReg = TmpReg;
387 assert (!IndexReg && "BaseReg/IndexReg already set!");
419 // If we already have a BaseReg, then assume this is the IndexReg with
421 if (!BaseReg) {
422 BaseReg
831 CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg, StringRef &ErrMsg) argument
1159 CreateMemForInlineAsm( unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier, InlineAsmIdentifierInfo &Info) argument
1439 int BaseReg = SM.getBaseReg(); local
2054 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; local
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