Searched refs:CHIPSET (Results 1 - 22 of 22) sorted by relevance

/external/mesa3d/include/pci_ids/
H A Di965_pci_ids.h0 CHIPSET(0x29A2, i965, "Intel(R) 965G")
2 CHIPSET(0x2992, i965, "Intel(R) 965Q")
3 CHIPSET(0x2982, i965, "Intel(R) 965G")
4 CHIPSET(0x2972, i965, "Intel(R) 946GZ")
5 CHIPSET(0x2A02, i965, "Intel(R) 965GM")
6 CHIPSET(0x2A12, i965, "Intel(R) 965GME/GLE")
7 CHIPSET(0x2A42, g4x, "Mobile Intel® GM45 Express Chipset")
8 CHIPSET(0x2E02, g4x, "Intel(R) Integrated Graphics Device")
9 CHIPSET(0x2E12, g4x, "Intel(R) Q45/Q43")
10 CHIPSET(
[all...]
H A Di810_pci_ids.h0 CHIPSET(0x7121, I810, i8xx)
2 CHIPSET(0x7123, I810_DC100, i8xx)
3 CHIPSET(0x7125, I810_E, i8xx)
4 CHIPSET(0x1132, I815, i8xx)
H A Dvmwgfx_pci_ids.h0 CHIPSET(0x0405, SVGAII, SVGAII)
H A Dradeon_pci_ids.h0 CHIPSET(0x4C57, RADEON_LW, RV200)
2 CHIPSET(0x4C58, RADEON_LX, RV200)
3 CHIPSET(0x4C59, RADEON_LY, RV100)
4 CHIPSET(0x4C5A, RADEON_LZ, RV100)
5 CHIPSET(0x5144, RADEON_QD, R100)
6 CHIPSET(0x5145, RADEON_QE, R100)
7 CHIPSET(0x5146, RADEON_QF, R100)
8 CHIPSET(0x5147, RADEON_QG, R100)
9 CHIPSET(0x5159, RADEON_QY, RV100)
10 CHIPSET(
[all...]
H A Di915_pci_ids.h0 CHIPSET(0x3577, I830_M, "Intel(R) 830M")
2 CHIPSET(0x2562, 845_G, "Intel(R) 845G")
3 CHIPSET(0x3582, I855_GM, "Intel(R) 852GM/855GM")
4 CHIPSET(0x2572, I865_G, "Intel(R) 865G")
5 CHIPSET(0x2582, I915_G, "Intel(R) 915G")
6 CHIPSET(0x258A, E7221_G, "Intel(R) E7221G (i915)")
7 CHIPSET(0x2592, I915_GM, "Intel(R) 915GM")
8 CHIPSET(0x2772, I945_G, "Intel(R) 945G")
9 CHIPSET(0x27A2, I945_GM, "Intel(R) 945GM")
10 CHIPSET(
[all...]
H A Dr600_pci_ids.h0 CHIPSET(0x9400, R600_9400, R600)
2 CHIPSET(0x9401, R600_9401, R600)
3 CHIPSET(0x9402, R600_9402, R600)
4 CHIPSET(0x9403, R600_9403, R600)
5 CHIPSET(0x9405, R600_9405, R600)
6 CHIPSET(0x940A, R600_940A, R600)
7 CHIPSET(0x940B, R600_940B, R600)
8 CHIPSET(0x940F, R600_940F, R600)
10 CHIPSET(0x94C0, RV610_94C0, RV610)
11 CHIPSET(
[all...]
H A Dr300_pci_ids.h0 CHIPSET(0x4144, R300_AD, R300)
2 CHIPSET(0x4145, R300_AE, R300)
3 CHIPSET(0x4146, R300_AF, R300)
4 CHIPSET(0x4147, R300_AG, R300)
5 CHIPSET(0x4E44, R300_ND, R300)
6 CHIPSET(0x4E45, R300_NE, R300)
7 CHIPSET(0x4E46, R300_NF, R300)
8 CHIPSET(0x4E47, R300_NG, R300)
10 CHIPSET(0x4E48, R350_NH, R350)
11 CHIPSET(
[all...]
H A Dvirtio_gpu_pci_ids.h0 CHIPSET(0x0010, VIRTGL, VIRTGL)
2 CHIPSET(0x1050, VIRTGL, VIRTGL)
H A Dradeonsi_pci_ids.h0 CHIPSET(0x6780, TAHITI_6780, TAHITI)
2 CHIPSET(0x6784, TAHITI_6784, TAHITI)
3 CHIPSET(0x6788, TAHITI_6788, TAHITI)
4 CHIPSET(0x678A, TAHITI_678A, TAHITI)
5 CHIPSET(0x6790, TAHITI_6790, TAHITI)
6 CHIPSET(0x6791, TAHITI_6791, TAHITI)
7 CHIPSET(0x6792, TAHITI_6792, TAHITI)
8 CHIPSET(0x6798, TAHITI_6798, TAHITI)
9 CHIPSET(0x6799, TAHITI_6799, TAHITI)
10 CHIPSET(
[all...]
H A Dr200_pci_ids.h0 CHIPSET(0x5148, R200_QH, R200)
2 CHIPSET(0x514C, R200_QL, R200)
3 CHIPSET(0x514D, R200_QM, R200)
4 CHIPSET(0x4242, R200_BB, R200)
6 CHIPSET(0x4966, RV250_If, RV250)
7 CHIPSET(0x4967, RV250_Ig, RV250)
8 CHIPSET(0x4C64, RV250_Ld, RV250)
9 CHIPSET(0x4C66, RV250_Lf, RV250)
10 CHIPSET(0x4C67, RV250_Lg, RV250)
12 CHIPSET(
[all...]
/external/libdrm/radeon/
H A Dr600_pci_ids.h0 CHIPSET(0x9400, R600_9400, R600)
2 CHIPSET(0x9401, R600_9401, R600)
3 CHIPSET(0x9402, R600_9402, R600)
4 CHIPSET(0x9403, R600_9403, R600)
5 CHIPSET(0x9405, R600_9405, R600)
6 CHIPSET(0x940A, R600_940A, R600)
7 CHIPSET(0x940B, R600_940B, R600)
8 CHIPSET(0x940F, R600_940F, R600)
10 CHIPSET(0x94C0, RV610_94C0, RV610)
11 CHIPSET(
[all...]
H A Dradeon_surface.c143 #define CHIPSET(pci_id, name, fam) case pci_id: surf_man->family = CHIP_##fam; break; macro
145 #undef CHIPSET macro
/external/mesa3d/src/loader/
H A Dpci_id_driver_map.h15 #define CHIPSET(chip, desc, name) chip, macro
17 #undef CHIPSET macro
21 #define CHIPSET(chip, family, name) chip, macro
23 #undef CHIPSET macro
27 #define CHIPSET(chip, name, family) chip, macro
29 #undef CHIPSET macro
33 #define CHIPSET(chip, name, family) chip, macro
35 #undef CHIPSET macro
39 #define CHIPSET(chip, name, family) chip, macro
41 #undef CHIPSET macro
45 #define CHIPSET macro
47 #undef CHIPSET macro
51 #define CHIPSET macro
53 #undef CHIPSET macro
57 #define CHIPSET macro
59 #undef CHIPSET macro
63 #define CHIPSET macro
65 #undef CHIPSET macro
[all...]
/external/mesa3d/src/mesa/drivers/dri/r200/
H A Dradeon_chipset.h11 #define CHIPSET(id, name, family) PCI_CHIP_##name = id, macro
17 #undef CHIPSET macro
/external/mesa3d/src/mesa/drivers/dri/radeon/
H A Dradeon_chipset.h11 #define CHIPSET(id, name, family) PCI_CHIP_##name = id, macro
17 #undef CHIPSET macro
/external/mesa3d/src/intel/common/
H A Dgen_device_info.c556 #undef CHIPSET macro
557 #define CHIPSET(id, family, name) \ macro
591 #undef CHIPSET macro
592 #define CHIPSET(id, family, name) case id: return name; macro
/external/mesa3d/src/gallium/drivers/r300/
H A Dr300_chipset.c69 #define CHIPSET(pci_id, name, chipfamily) \ macro
74 #undef CHIPSET macro
/external/mesa3d/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_winsys.c200 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break; macro
202 #undef CHIPSET macro
204 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break; macro
206 #undef CHIPSET macro
208 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break; macro
210 #undef CHIPSET macro
/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_winsys.c184 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; break; macro
186 #undef CHIPSET macro
/external/mesa3d/src/gallium/winsys/amdgpu/drm/
H A Damdgpu_winsys.c205 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; break; macro
207 #undef CHIPSET macro
/external/mesa3d/src/mesa/drivers/dri/i915/
H A Dintel_context.c73 #undef CHIPSET macro
74 #define CHIPSET(id, symbol, str) case id: chipset = str; break; macro
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_context.c104 #undef CHIPSET macro
105 #define CHIPSET(id, symbol, str) case id: chipset = str; break; macro

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