/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMLoadStoreOptimizer.cpp | 95 MemOpQueue &MemOps, 111 unsigned Scratch, MemOpQueue &MemOps, 114 void AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps); 365 // MergeOpsUpdate - call MergeOps and update MemOps and merges accordingly on 441 unsigned Scratch, MemOpQueue &MemOps, 444 int Offset = MemOps[SIndex].Offset; 447 MachineBasicBlock::iterator Loc = MemOps[SIndex].MBBI; 474 for (unsigned i = SIndex+1, e = MemOps.size(); i != e; ++i) { 475 int NewOffset = MemOps[i].Offset; 476 const MachineOperand &MO = MemOps[ 438 MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base, int Opcode, unsigned Size, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, MemOpQueue &MemOps, SmallVector<MachineBasicBlock::iterator, 4> &Merges) argument 1006 AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps) argument 1181 MemOpQueue MemOps; local 1454 IsSafeAndProfitableToMove(bool isLd, unsigned Base, MachineBasicBlock::iterator I, MachineBasicBlock::iterator E, SmallPtrSet<MachineInstr*, 4> &MemOps, SmallSet<unsigned, 4> &MemRegs, const TargetRegisterInfo *TRI) argument 1638 SmallPtrSet<MachineInstr*, 4> MemOps; local [all...] |
H A D | ARMISelLowering.cpp | 2453 SmallVector<SDValue, 4> MemOps; local 2467 MemOps.push_back(Store); 2471 if (!MemOps.empty()) 2473 &MemOps[0], MemOps.size());
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/external/llvm/lib/Target/ARM/ |
H A D | ARMLoadStoreOptimizer.cpp | 161 void FormCandidates(const MemOpQueue &MemOps); 813 /// Call MergeOps and update MemOps and merges accordingly on success. 956 void ARMLoadStoreOpt::FormCandidates(const MemOpQueue &MemOps) { argument 957 const MachineInstr *FirstMI = MemOps[0].MI; 963 unsigned EIndex = MemOps.size(); 966 const MachineInstr *MI = MemOps[SIndex].MI; 967 int Offset = MemOps[SIndex].Offset; 999 int NewOffset = MemOps[I].Offset; 1002 const MachineOperand &MO = getLoadStoreRegOp(*MemOps[I].MI); 1029 unsigned Position = MemOps[ [all...] |
H A D | ARMISelLowering.cpp | 3154 SmallVector<SDValue, 4> MemOps; local 3164 MemOps.push_back(Store); 3168 if (!MemOps.empty()) 3169 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1302 SmallVector<SDValue, 4> MemOps; local 1382 MemOps.push_back(Store); 1410 MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV, 1421 if (!MemOps.empty()) { 1422 MemOps.push_back(Chain); 1423 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAG.cpp | 4183 static bool FindOptimalMemOpLowering(std::vector<EVT> &MemOps, argument 4278 MemOps.push_back(VT); 4308 std::vector<EVT> MemOps; local 4324 if (!FindOptimalMemOpLowering(MemOps, Limit, Size, 4334 Type *Ty = MemOps[0].getTypeForEVT(*DAG.getContext()); 4354 unsigned NumMemOps = MemOps.size(); 4357 EVT VT = MemOps[i]; 4424 std::vector<EVT> MemOps; local 4437 if (!FindOptimalMemOpLowering(MemOps, Limit, Size, 4446 Type *Ty = MemOps[ 4520 std::vector<EVT> MemOps; local [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAG.cpp | 3345 static bool FindOptimalMemOpLowering(std::vector<EVT> &MemOps, argument 3407 MemOps.push_back(VT); 3430 std::vector<EVT> MemOps; local 3446 if (!FindOptimalMemOpLowering(MemOps, Limit, Size, 3453 Type *Ty = MemOps[0].getTypeForEVT(*DAG.getContext()); 3464 unsigned NumMemOps = MemOps.size(); 3467 EVT VT = MemOps[i]; 3523 std::vector<EVT> MemOps; local 3536 if (!FindOptimalMemOpLowering(MemOps, Limit, Size, 3542 Type *Ty = MemOps[ 3601 std::vector<EVT> MemOps; local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1153 SmallVector<SDValue, 4> MemOps; local 1173 MemOps.push_back(Store); 1175 if (!MemOps.empty()) 1177 &MemOps[0], MemOps.size());
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 1760 SmallVector<SDValue, 8> MemOps; local 1805 MemOps.push_back(Store); 1824 MemOps.push_back(Store); 1832 if (!MemOps.empty()) 1834 MVT::Other, &MemOps[0], MemOps.size()); 1939 SmallVector<SDValue, 8> MemOps; local 1993 MemOps.push_back(Store); 2017 MemOps.push_back(Store); 2190 MemOps [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
H A D | SPUISelLowering.cpp | 1218 SmallVector<SDValue, 79-3+1> MemOps; local 1230 MemOps.push_back(Store); 1235 if (!MemOps.empty()) 1237 &MemOps[0], MemOps.size());
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 3031 SmallVector<SDValue, 8> MemOps; local 3077 MemOps.push_back(Store); 3096 MemOps.push_back(Store); 3104 if (!MemOps.empty()) 3105 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); 3195 SmallVector<SDValue, 8> MemOps; local 3299 MemOps.push_back(Store); 3326 MemOps.push_back(Store); 3531 MemOps.push_back(Store); 3538 if (!MemOps 3640 SmallVector<SDValue, 8> MemOps; local [all...] |
/external/llvm/lib/CodeGen/ |
H A D | MachineScheduler.cpp | 1381 void clusterNeighboringMemOps(ArrayRef<SUnit *> MemOps, ScheduleDAGMI *DAG); 1399 ArrayRef<SUnit *> MemOps, ScheduleDAGMI *DAG) { 1401 for (unsigned Idx = 0, End = MemOps.size(); Idx != End; ++Idx) { 1402 SUnit *SU = MemOps[Idx]; 1450 // Map each store chain to a set of dependent MemOps. 1398 clusterNeighboringMemOps( ArrayRef<SUnit *> MemOps, ScheduleDAGMI *DAG) argument
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 2645 SmallVector<SDValue, 8> MemOps; local 2667 MemOps.push_back(Store); 2697 MemOps.push_back(Store); 2706 if (!MemOps.empty()) { 2707 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps); 4234 SmallVector<SDValue, 4> MemOps; local 4238 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList, 4253 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr, 4268 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr, 4275 MemOps [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 1906 SmallVector<SDValue, 8> MemOps; local 1921 MemOps.push_back(Store); 1945 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 1950 if (!MemOps.empty()) 1952 &MemOps[0], MemOps.size()); 9007 SmallVector<SDValue, 8> MemOps; local 9014 MemOps.push_back(Store); 9023 MemOps.push_back(Store); 9033 MemOps [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 988 SDValue MemOps[SystemZ::NumArgFPRs]; local 996 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN, 1002 makeArrayRef(&MemOps[NumFixedFPRs], 2820 SDValue MemOps[NumFields]; 2827 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr, 2832 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1089 SmallVector<SDValue, 8> MemOps; local 1190 if (!MemOps.empty()) 1191 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 2771 SmallVector<SDValue, 8> MemOps; local 2784 MemOps.push_back(Store); 2799 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2803 if (!MemOps.empty()) 2804 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); 16912 SmallVector<SDValue, 8> MemOps; local 16919 MemOps.push_back(Store); 16927 MemOps.push_back(Store); 16935 MemOps.push_back(Store); 16943 MemOps [all...] |