Searched refs:RSP (Results 1 - 25 of 44) sorted by relevance

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/external/llvm/test/MC/X86/
H A Dintel-syntax-2.s6 mov DWORD PTR [RSP - 4], 257
13 mov DWORD PTR [RSP - 4], 255
H A Dintel-syntax-encoding.s25 mov QWORD PTR [RSP - 16], RAX
H A Dintel-syntax.s11 mov DWORD PTR [RSP - 4], 257
13 mov DWORD PTR [RSP + 4], 258
15 mov QWORD PTR [RSP - 16], 123
17 mov BYTE PTR [RSP - 17], 97
19 mov EAX, DWORD PTR [RSP - 4]
21 mov RAX, QWORD PTR [RSP]
23 mov DWORD PTR [RSP - 4], -4
27 mov EAX, DWORD PTR [RSP + 4*RAX - 24]
/external/libunwind/src/x86_64/
H A DGstash_frame.c42 rs->reg[RSP].where, rs->reg[RSP].val, DWARF_GET_LOC(d->loc[RSP]));
45 - CFA is register-relative offset off RBP or RSP;
48 - RSP is unsaved or saved at CFA+offset, offset != -1. */
52 || rs->reg[DWARF_CFA_REG_COLUMN].val == RSP)
60 && (rs->reg[RSP].where == DWARF_WHERE_UNDEF
61 || rs->reg[RSP].where == DWARF_WHERE_SAME
62 || (rs->reg[RSP].where == DWARF_WHERE_CFAREL
63 && labs(rs->reg[RSP]
[all...]
H A DGget_save_loc.c41 case UNW_X86_64_RSP: loc = c->dwarf.loc[RSP]; break;
H A Dunwind_i.h46 #define RSP 7 macro
H A Dinit.h56 c->dwarf.loc[RSP] = REG_INIT_LOC(c, rsp, RSP);
H A DGos-freebsd.c118 c->dwarf.loc[RSP] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_RSP, 0);
H A DGstep.c130 /* Like regular frame, CFA = RSP+8, RA = [CFA-8], no regs saved. */
198 c->dwarf.loc[RSP] = rsp_loc;
/external/strace/linux/x86_64/
H A Duserent.h20 XLAT(8*RSP),
/external/kernel-headers/original/uapi/asm-x86/asm/
H A Dptrace-abi.h57 #define RSP 152 macro
/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86CompilationCallback_Win64.asm20 ; Save RSP.
53 ; Restore RSP.
H A DX86RegisterInfo.cpp69 StackPtr = X86::RSP;
394 Reserved.set(X86::RSP);
695 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
732 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
768 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
804 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
805 return X86::RSP;
H A DX86GenRegisterInfo.inc133 RSP = 114,
302 const unsigned ESP_Overlaps[] = { X86::ESP, X86::RSP, X86::SP, X86::SPL, 0 };
362 const unsigned RSP_Overlaps[] = { X86::RSP, X86::ESP, X86::SP, X86::SPL, 0 };
365 const unsigned SP_Overlaps[] = { X86::SP, X86::ESP, X86::RSP, X86::SPL, 0 };
366 const unsigned SPL_Overlaps[] = { X86::SPL, X86::ESP, X86::RSP, X86::SP, 0 };
516 const unsigned ESP_SuperRegsSet[] = { X86::RSP, 0 };
544 const unsigned SP_SuperRegsSet[] = { X86::ESP, X86::RSP, 0 };
545 const unsigned SPL_SuperRegsSet[] = { X86::SP, X86::ESP, X86::RSP, 0 };
679 { "RSP", RSP_Overlaps, RSP_SubRegsSet, Empty_SuperRegsSet },
740 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X8
[all...]
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp109 X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBP, X86::RSP,
187 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
291 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
319 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
356 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
392 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
428 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
429 return X86::RSP;
/external/lzma/Asm/x86/
H A D7zAsm.asm70 r4 equ RSP
/external/valgrind/coregrind/m_sigframe/
H A Dsigframe-amd64-darwin.c108 SC2(__rsp,RSP);
136 SC2(RSP,__rsp);
226 "next RIP=%#lx, next RSP=%#lx\n",
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmInstrumentation.cpp85 // * Instrumented memory operand can have RSP as a base or an index
88 // already stored on stack and RSP was modified.
90 // RSP is used as a frame register. So, we need to select some
115 bool IsStackReg(unsigned Reg) { return Reg == X86::RSP || Reg == X86::ESP; }
798 if (FrameReg == X86::RSP) {
836 if (FrameReg == X86::RSP)
858 X86Operand::CreateMem(getPointerWidth(), 0, Disp, X86::RSP, 0, 1, member in class:llvm::__anon13326::X86AddressSanitizer64::X86
860 EmitLEA(*Op, 64, X86::RSP, Out);
870 .addReg(X86::RSP)
871 .addReg(X86::RSP)
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp149 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
322 MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
326 MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
/external/google-breakpad/src/common/android/
H A Dbreakpad_getcontext_unittest.cc136 CHECK_REG(RSP);
/external/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp503 // We need to exit with RSP modified by this amount and execute suitable
505 // All stack probing must be done without modifying RSP.
510 // CopyReg = RSP
523 // RSP = RSP - RAX
585 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
588 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
601 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP);
633 // final RSP value. Add code to loopMBB to decrement LimitReg page-by-page
665 X86::RSP, fals
[all...]
H A DX86RegisterInfo.cpp70 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
437 for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
/external/llvm/include/llvm/DebugInfo/CodeView/
H A DCodeView.h517 RSP = 335, member in class:llvm::codeview::CallingConvention::ClassOptions::FrameProcedureOptions::FunctionOptions::HfaKind::MemberAccess::MethodKind::MethodOptions::ModifierOptions::PointerKind::PointerMode::PointerOptions::PointerToMemberRepresentation::VFTableSlotKind::WindowsRTClassKind::ExportFlags::RegisterId
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h183 ENTRY(RSP) \
/external/valgrind/VEX/auxprogs/
H A Dgenoffsets.c109 GENOFFSET(AMD64,amd64,RSP);

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