Searched refs:Shift1Reg (Results 1 - 2 of 2) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 4751 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); local
4795 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4798 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
5073 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); local
5127 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5130 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 8542 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); local
8586 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8589 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
9257 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); local
9311 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
9314 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
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Completed in 138 milliseconds