| /external/llvm/lib/CodeGen/ |
| H A D | RenameIndependentSubregs.cpp | 182 unsigned SubRegIdx = MO.getSubReg(); local
183 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
225 unsigned SubRegIdx = MO.getSubReg(); local
226 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
336 unsigned SubRegIdx = MO.getSubReg(); local
337 if (SubRegIdx == 0)
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| H A D | RegisterPressure.cpp | 492 unsigned SubRegIdx = MO.getSubReg();
495 pushRegLanes(Reg, SubRegIdx, RegOpers.Uses);
500 SubRegIdx = 0;
504 pushRegLanes(Reg, SubRegIdx, RegOpers.DeadDefs);
506 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs);
510 void pushRegLanes(unsigned Reg, unsigned SubRegIdx,
513 LaneBitmask LaneMask = SubRegIdx != 0
514 ? TRI.getSubRegIndexLaneMask(SubRegIdx)
1192 unsigned SubRegIdx = MO.getSubReg();
1193 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
[all...] |
| H A D | StackMaps.cpp | 145 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg()); local
146 if (SubRegIdx)
147 Offset = TRI->getSubRegIdxOffset(SubRegIdx);
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| H A D | VirtRegMap.cpp | 340 unsigned SubRegIdx = MO.getSubReg(); local
341 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
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| H A D | MachineVerifier.cpp | 1224 unsigned SubRegIdx = MO->getSubReg(); local
1225 LaneBitmask MOMask = SubRegIdx != 0
1226 ? TRI->getSubRegIndexLaneMask(SubRegIdx)
1325 unsigned SubRegIdx = MO->getSubReg(); local
1326 LaneBitmask MOMask = SubRegIdx != 0
1327 ? TRI->getSubRegIndexLaneMask(SubRegIdx)
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| H A D | RegisterCoalescer.cpp | 214 MachineOperand &MO, unsigned SubRegIdx);
1217 MachineOperand &MO, unsigned SubRegIdx) {
1218 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubRegIdx);
1216 addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx, MachineOperand &MO, unsigned SubRegIdx) argument
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| /external/llvm/lib/Target/X86/ |
| H A D | X86FixupBWInsts.cpp | 190 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); local
196 if (SubRegIdx == X86::sub_8bit_hi)
202 if (SubRegIdx == X86::sub_8bit) {
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 655 unsigned SubRegIdx = (is32Bit ? local
660 CurDAG->getTargetConstant(SubRegIdx,
669 unsigned SubRegIdx = (is32Bit ? local
674 CurDAG->getTargetConstant(SubRegIdx,
715 unsigned SubRegIdx = (is32Bit ? local
720 CurDAG->getTargetConstant(SubRegIdx, MVT::i32));
740 unsigned SubRegIdx = (is32Bit ? local
745 CurDAG->getTargetConstant(SubRegIdx,
753 unsigned SubRegIdx = (is32Bit ? local
758 CurDAG->getTargetConstant(SubRegIdx,
[all...] |
| /external/llvm/include/llvm/Target/ |
| H A D | TargetRegisterInfo.h | 1102 unsigned SubRegIdx = 0);
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 155 unsigned SubRegIdx);
157 unsigned SubRegIdx);
1135 unsigned SubRegIdx) {
1149 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
1156 unsigned Opc, unsigned SubRegIdx) {
1180 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
1134 SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc, unsigned SubRegIdx) argument
1155 SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc, unsigned SubRegIdx) argument
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| /external/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 212 unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue(); local
214 SubRegIdx);
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 3440 SDValue SubRegIdx = local
3443 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
3453 SDValue SubRegIdx = local
3456 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 3227 unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0; local
3284 .addReg(LaneReg, 0, SubRegIdx);
3313 .addReg(LaneTmp2, 0, SubRegIdx);
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