Searched refs:UseIdx (Results 1 - 25 of 44) sorted by relevance

12

/external/llvm/include/llvm/MC/
H A DMCInstrItineraries.h185 /// operand index UseIdx.
187 unsigned UseClass, unsigned UseIdx) const {
197 if ((FirstUseIdx + UseIdx) >= LastUseIdx)
201 Forwardings[FirstUseIdx + UseIdx];
208 unsigned UseClass, unsigned UseIdx) const {
216 int UseCycle = getOperandCycle(UseClass, UseIdx);
222 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
H A DMCSubtargetInfo.h136 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, argument
143 if (I->UseIdx < UseIdx)
145 if (I->UseIdx > UseIdx)
H A DMCSchedule.h84 /// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by
87 unsigned UseIdx; member in struct:llvm::MCReadAdvanceEntry
92 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
/external/swiftshader/third_party/LLVM/include/llvm/MC/
H A DMCInstrItineraries.h198 /// itinerary class UseClass, operand index UseIdx.
200 unsigned UseClass, unsigned UseIdx) const {
210 if ((FirstUseIdx + UseIdx) >= LastUseIdx)
214 Forwardings[FirstUseIdx + UseIdx];
221 unsigned UseClass, unsigned UseIdx) const {
229 int UseCycle = getOperandCycle(UseClass, UseIdx);
235 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
/external/swiftshader/third_party/LLVM/lib/Target/
H A DTargetInstrInfo.cpp67 const MachineInstr *UseMI, unsigned UseIdx) const {
73 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
79 SDNode *UseNode, unsigned UseIdx) const {
90 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
/external/llvm/lib/CodeGen/
H A DTargetSchedule.cpp144 unsigned UseIdx = 0; local
148 ++UseIdx;
150 return UseIdx;
202 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); local
203 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
H A DLiveRangeEdit.cpp84 /// OrigIdx are also available with the same value at UseIdx.
87 SlotIndex UseIdx) const {
89 UseIdx = UseIdx.getRegSlot(true);
110 if (SlotIndex::isSameInstr(OrigIdx, UseIdx))
113 if (OVNI != li.getVNInfoAt(UseIdx))
120 SlotIndex UseIdx, bool cheapAsAMove) {
137 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
119 canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx, bool cheapAsAMove) argument
H A DLiveRangeCalc.cpp186 SlotIndex UseIdx; local
191 UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo+1).getMBB());
203 UseIdx = Indexes->getInstructionIndex(*MI).getRegSlot(isEarlyClobber);
208 extend(LR, UseIdx, Reg);
H A DRegisterCoalescer.cpp213 void addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
705 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI); local
706 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
759 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true); local
760 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
780 SlotIndex DefIdx = UseIdx.getRegSlot();
1193 SlotIndex UseIdx = LIS->getInstructionIndex(MI); local
1201 if (SR.liveAt(UseIdx)) {
1207 isLive = DstLI.liveAt(UseIdx);
1211 DEBUG(dbgs() << "\tnew undef: " << UseIdx << '\
1216 addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx, MachineOperand &MO, unsigned SubRegIdx) argument
1256 SlotIndex UseIdx = LIS->getInstructionIndex(MI).getRegSlot(true); local
1305 SlotIndex UseIdx = MIIdx.getRegSlot(true); local
[all...]
H A DTargetInstrInfo.cpp983 SDNode *UseNode, unsigned UseIdx) const {
994 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1072 unsigned UseIdx) const {
1075 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1096 unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const {
1106 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, *UseMI, UseIdx);
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DLiveRangeEdit.cpp81 /// OrigIdx are also available with the same value at UseIdx.
84 SlotIndex UseIdx,
87 UseIdx = UseIdx.getUseIndex();
105 if (OVNI != li.getVNInfoAt(UseIdx))
112 SlotIndex UseIdx,
136 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx, lis))
82 allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx, SlotIndex UseIdx, LiveIntervals &lis) argument
111 canRematerializeAt(Remat &RM, SlotIndex UseIdx, bool cheapAsAMove, LiveIntervals &lis) argument
H A DLiveRangeEdit.h80 /// OrigIdx are also available with the same value at UseIdx.
82 SlotIndex UseIdx, LiveIntervals &lis);
156 /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI.
159 SlotIndex UseIdx,
H A DSplitKit.h306 /// defFromParent - Define Reg from ParentVNI at UseIdx using either
310 SlotIndex UseIdx,
H A DInlineSpiller.cpp836 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getUseIndex(); local
837 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
846 DEBUG(dbgs() << UseIdx << '\t' << *MI);
858 if (!Edit->canRematerializeAt(RM, UseIdx, false, LIS)) {
860 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
874 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
907 DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI);
910 NewLI.addRange(LiveRange(DefIdx, UseIdx.getDefIndex(), DefVNI));
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMBaseInstrInfo.h210 const MachineInstr *UseMI, unsigned UseIdx) const;
214 SDNode *UseNode, unsigned UseIdx) const;
233 unsigned UseIdx, unsigned UseAlign) const;
237 unsigned UseIdx, unsigned UseAlign) const;
242 unsigned UseIdx, unsigned UseAlign) const;
253 const MachineInstr *UseMI, unsigned UseIdx) const;
H A DARMBaseInstrInfo.cpp2161 unsigned UseIdx, unsigned UseAlign) const {
2162 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2164 return ItinData->getOperandCycle(UseClass, UseIdx);
2201 unsigned UseIdx, unsigned UseAlign) const {
2202 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2204 return ItinData->getOperandCycle(UseClass, UseIdx);
2231 unsigned UseIdx, unsigned UseAlign) const {
2235 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2236 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2286 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
[all...]
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h284 unsigned UseIdx) const override;
287 SDNode *UseNode, unsigned UseIdx) const override;
317 unsigned UseIdx, unsigned UseAlign) const;
321 unsigned UseIdx, unsigned UseAlign) const;
326 unsigned UseIdx, unsigned UseAlign) const;
332 const MachineInstr &UseMI, unsigned UseIdx,
348 unsigned UseIdx) const override;
H A DARMBaseInstrInfo.cpp3263 unsigned UseIdx, unsigned UseAlign) const {
3264 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3266 return ItinData->getOperandCycle(UseClass, UseIdx);
3303 unsigned UseIdx, unsigned UseAlign) const {
3304 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3306 return ItinData->getOperandCycle(UseClass, UseIdx);
3333 unsigned UseIdx, unsigned UseAlign) const {
3337 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3338 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3388 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3260 getVSTMUseCycle(const InstrItineraryData *ItinData, const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const argument
3300 getSTMUseCycle(const InstrItineraryData *ItinData, const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const argument
3329 getOperandLatency(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID, unsigned UseIdx, unsigned UseAlign) const argument
3463 getBundledUseMI(const TargetRegisterInfo *TRI, const MachineInstr &MI, unsigned Reg, unsigned &UseIdx, unsigned &Dist) argument
3709 getOperandLatencyImpl( const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj, const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI, unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const argument
[all...]
/external/llvm/include/llvm/CodeGen/
H A DLiveRangeEdit.h91 /// OrigIdx are also available with the same value at UseIdx.
93 SlotIndex UseIdx) const;
202 /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI.
204 bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx,
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h121 unsigned UseIdx) const override;
124 SDNode *UseNode, unsigned UseIdx) const override {
126 UseNode, UseIdx);
H A DPPCVSXSwapRemoval.cpp672 int UseIdx = SwapMap[&UseMI]; local
674 if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad ||
675 SwapVector[UseIdx].IsStore) {
683 DEBUG(dbgs() << " use " << UseIdx << ": ");
715 int UseIdx = SwapMap[&UseMI]; local
717 if (SwapVector[UseIdx].VSEMI->getOpcode() != MI->getOpcode()) {
725 DEBUG(dbgs() << " use " << UseIdx << ": ");
726 DEBUG(SwapVector[UseIdx].VSEMI->dump());
756 int UseIdx local
[all...]
H A DPPCInstrInfo.cpp144 unsigned UseIdx) const {
146 UseMI, UseIdx);
1235 unsigned UseIdx; local
1236 for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
1237 if (UseMI.getOperand(UseIdx).isReg() &&
1238 UseMI.getOperand(UseIdx).getReg() == Reg)
1241 assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
1242 assert(UseIdx < UseMCI
[all...]
/external/swiftshader/third_party/LLVM/include/llvm/Target/
H A DTargetInstrInfo.h645 const MachineInstr *UseMI, unsigned UseIdx) const;
649 SDNode *UseNode, unsigned UseIdx) const;
674 const MachineInstr *UseMI, unsigned UseIdx) const {
/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h1222 SDNode *UseNode, unsigned UseIdx) const;
1235 unsigned UseIdx) const;
1247 /// DefIdx or UseIdx to compute min latency.
1251 unsigned UseIdx) const;
1284 unsigned UseIdx) const {
/external/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp958 // Entries must be sorted first by UseIdx then by WriteResourceID.
959 for (unsigned UseIdx = 0, EndIdx = Reads.size();
960 UseIdx != EndIdx; ++UseIdx) {
962 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
983 RAEntry.UseIdx = UseIdx;
1088 OS << "\n// {UseIdx, WriteResourceID, Cycles}\n"
1095 OS << " {" << RAEntry.UseIdx << ", "

Completed in 636 milliseconds

12