Searched refs:VRegs (Results 1 - 12 of 12) sorted by relevance
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64CallLowering.h | 33 const SmallVectorImpl<unsigned> &VRegs) const override;
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H A D | AArch64CallLowering.cpp | 58 const SmallVectorImpl<unsigned> &VRegs) const { 85 MIRBuilder.buildInstr(TargetOpcode::COPY, VRegs[i], VA.getLocReg());
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/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUCallLowering.cpp | 39 const SmallVectorImpl<unsigned> &VRegs) const {
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H A D | AMDGPUCallLowering.h | 33 const SmallVectorImpl<unsigned> &VRegs) const override;
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/external/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | CallLowering.h | 56 /// must end up in the related virtual register described by VRegs. 57 /// In other words, the first argument should end up in VRegs[0], 58 /// the second in VRegs[1], and so on. 66 const SmallVectorImpl<unsigned> &VRegs) const {
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | RegAllocBasic.cpp | 191 LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg]; local 192 PhysReg2LiveUnion[PhysReg].verify(VRegs); 195 assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions"); 196 VisitedVRegs |= VRegs;
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.h | 136 SmallVectorImpl<unsigned> &VRegs) const;
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H A D | HexagonFrameLowering.cpp | 1860 SmallVectorImpl<unsigned> &VRegs) const {
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 813 SmallVector<CalleeSavedInfo, 18> VRegs; local 850 VRegs.push_back(CSI[i]); 963 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 964 int FI = VRegs[i].getFrameIdx();
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/external/llvm/lib/Target/PowerPC/Disassembler/ |
H A D | PPCDisassembler.cpp | 92 static const unsigned VRegs[] = { variable 248 return decodeRegisterClass(Inst, RegNo, VRegs);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 1485 SmallVector<CalleeSavedInfo, 18> VRegs; local 1521 VRegs.push_back(CSI[i]); 1661 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1662 int FI = VRegs[i].getFrameIdx();
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/external/llvm/lib/Target/PowerPC/AsmParser/ |
H A D | PPCAsmParser.cpp | 86 static const MCPhysReg VRegs[32] = { variable 601 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); 1297 RegNo = VRegs[IntVal];
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