Searched refs:VRegs (Results 1 - 12 of 12) sorted by relevance

/external/llvm/lib/Target/AArch64/
H A DAArch64CallLowering.h33 const SmallVectorImpl<unsigned> &VRegs) const override;
H A DAArch64CallLowering.cpp58 const SmallVectorImpl<unsigned> &VRegs) const {
85 MIRBuilder.buildInstr(TargetOpcode::COPY, VRegs[i], VA.getLocReg());
/external/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp39 const SmallVectorImpl<unsigned> &VRegs) const {
H A DAMDGPUCallLowering.h33 const SmallVectorImpl<unsigned> &VRegs) const override;
/external/llvm/include/llvm/CodeGen/GlobalISel/
H A DCallLowering.h56 /// must end up in the related virtual register described by VRegs.
57 /// In other words, the first argument should end up in VRegs[0],
58 /// the second in VRegs[1], and so on.
66 const SmallVectorImpl<unsigned> &VRegs) const {
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DRegAllocBasic.cpp191 LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg]; local
192 PhysReg2LiveUnion[PhysReg].verify(VRegs);
195 assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions");
196 VisitedVRegs |= VRegs;
/external/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.h136 SmallVectorImpl<unsigned> &VRegs) const;
H A DHexagonFrameLowering.cpp1860 SmallVectorImpl<unsigned> &VRegs) const {
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp813 SmallVector<CalleeSavedInfo, 18> VRegs; local
850 VRegs.push_back(CSI[i]);
963 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
964 int FI = VRegs[i].getFrameIdx();
/external/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp92 static const unsigned VRegs[] = { variable
248 return decodeRegisterClass(Inst, RegNo, VRegs);
/external/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp1485 SmallVector<CalleeSavedInfo, 18> VRegs; local
1521 VRegs.push_back(CSI[i]);
1661 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1662 int FI = VRegs[i].getFrameIdx();
/external/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp86 static const MCPhysReg VRegs[32] = { variable
601 Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
1297 RegNo = VRegs[IntVal];

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