Searched refs:enabled_mask (Results 1 - 25 of 27) sorted by relevance

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/external/mesa3d/src/gallium/drivers/radeon/
H A Dr600_streamout.c80 unsigned num_bufs = util_bitcount(rctx->streamout.enabled_mask);
81 unsigned num_bufs_appended = util_bitcount(rctx->streamout.enabled_mask &
119 unsigned enabled_mask = 0, append_bitmask = 0; local
133 enabled_mask |= 1 << i;
141 rctx->streamout.enabled_mask = enabled_mask;
345 rctx->streamout.hw_enabled_mask = rctx->streamout.enabled_mask |
346 (rctx->streamout.enabled_mask << 4) |
347 (rctx->streamout.enabled_mask << 8) |
348 (rctx->streamout.enabled_mask << 1
[all...]
H A Dr600_pipe_common.h471 unsigned enabled_mask; member in struct:r600_streamout
/external/mesa3d/src/gallium/drivers/virgl/
H A Dvirgl_context.h48 uint32_t enabled_mask; member in struct:virgl_textures_info
H A Dvirgl_context.c107 uint32_t remaining_mask = tinfo->enabled_mask;
705 remaining_mask = tinfo->enabled_mask & disable_mask;
729 tinfo->enabled_mask &= ~disable_mask;
730 tinfo->enabled_mask |= new_mask;
/external/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_descriptors.c343 unsigned mask = views->enabled_mask;
469 views->enabled_mask |= 1u << slot;
471 /* Since this can flush, it must be done after enabled_mask is
486 views->enabled_mask &= ~(1u << slot);
569 unsigned mask = samplers->views.enabled_mask;
617 uint mask = images->enabled_mask;
636 if (images->enabled_mask & (1u << slot)) {
643 images->enabled_mask &= ~(1u << slot);
753 images->enabled_mask |= 1u << slot;
757 /* Since this can flush, it must be done after enabled_mask i
[all...]
H A Dsi_state.h248 unsigned enabled_mask; member in struct:si_sampler_views
257 unsigned enabled_mask; member in struct:si_buffer_resources
H A Dsi_pipe.h162 unsigned enabled_mask; member in struct:si_images_info
H A Dsi_blit.c530 uint32_t mask = textures->views.enabled_mask;
571 uint32_t mask = images->enabled_mask;
/external/mesa3d/src/gallium/drivers/freedreno/a2xx/
H A Dfd2_emit.c57 uint32_t enabled_mask = constbuf->enabled_mask; local
63 constbuf->dirty_mask = enabled_mask;
66 while (enabled_mask) {
67 unsigned index = ffs(enabled_mask) - 1;
103 enabled_mask &= ~(1 << index);
/external/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_context.h79 uint32_t enabled_mask; member in struct:etna_vertexbuf_state
H A Detnaviv_state.c417 util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, num_buffers);
418 so->count = util_last_bit(so->enabled_mask);
/external/mesa3d/src/gallium/drivers/freedreno/
H A Dfreedreno_state.c104 so->enabled_mask &= ~(1 << index);
109 so->enabled_mask |= 1 << index;
223 util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, count);
224 so->count = util_last_bit(so->enabled_mask);
H A Dfreedreno_context.h71 uint32_t enabled_mask; member in struct:fd_constbuf_stateobj
78 uint32_t enabled_mask; member in struct:fd_vertexbuf_stateobj
H A Dfreedreno_draw.c139 foreach_bit(i, ctx->constbuf[PIPE_SHADER_VERTEX].enabled_mask)
141 foreach_bit(i, ctx->constbuf[PIPE_SHADER_FRAGMENT].enabled_mask)
145 foreach_bit(i, ctx->vtx.vertexbuf.enabled_mask) {
/external/mesa3d/src/gallium/drivers/ilo/
H A Dilo_state.h163 uint32_t enabled_mask; member in struct:ilo_vb_state
201 uint32_t enabled_mask; member in struct:ilo_cbuf_state
H A Dilo_state.c365 uint32_t upload_mask = cbuf->enabled_mask;
1573 cbuf->enabled_mask |= 1 << (index + i);
1579 cbuf->enabled_mask |= 1 << (index + i);
1585 cbuf->enabled_mask &= ~(1 << (index + i));
1598 cbuf->enabled_mask &= ~(1 << (index + i));
1907 &vec->vb.enabled_mask, buffers, start_slot, num_buffers);
2414 if (vec->vb.enabled_mask & (1 << i))
2469 uint32_t vb_mask = vec->vb.enabled_mask;
H A Dilo_shader.c247 if ((vec->cbuf[info->type].enabled_mask & 0x1) &&
/external/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_context.h193 uint32_t enabled_mask; member in struct:vc4_constbuf_stateobj
200 uint32_t enabled_mask; member in struct:vc4_vertexbuf_stateobj
H A Dvc4_state.c297 util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb,
299 so->count = util_last_bit(so->enabled_mask);
389 so->enabled_mask &= ~(1 << index);
399 so->enabled_mask |= 1 << index;
/external/mesa3d/src/gallium/drivers/r600/
H A Dr600_hw_context.c350 ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
358 constbuf->dirty_mask = constbuf->enabled_mask;
359 samplers->views.dirty_mask = samplers->views.enabled_mask;
360 samplers->states.dirty_mask = samplers->states.enabled_mask;
H A Dr600_state_common.c456 dst->states.enabled_mask &= ~disable_mask;
457 dst->states.dirty_mask &= dst->states.enabled_mask;
458 dst->states.enabled_mask |= new_mask;
460 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
582 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
583 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
584 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
625 remaining_mask = dst->views.enabled_mask & disable_mask;
660 (dst->states.enabled_mask & (1 << i)) &&
675 dst->views.enabled_mask
[all...]
H A Dr600_pipe.h352 uint32_t enabled_mask; member in struct:r600_samplerview_state
362 uint32_t enabled_mask; member in struct:r600_sampler_states
386 uint32_t enabled_mask; member in struct:r600_constbuf_state
394 uint32_t enabled_mask; /* non-NULL buffers */ member in struct:r600_vertexbuf_state
H A Dr600_blit.c82 rctx->blitter, util_last_bit(rctx->samplers[PIPE_SHADER_FRAGMENT].states.enabled_mask),
86 rctx->blitter, util_last_bit(rctx->samplers[PIPE_SHADER_FRAGMENT].views.enabled_mask),
H A Devergreen_compute.c155 state->enabled_mask |= 1 << vb_index;
/external/mesa3d/src/gallium/drivers/freedreno/ir3/
H A Dir3_shader.c494 uint32_t dirty_mask = constbuf->enabled_mask;
541 if ((constbuf->enabled_mask & (1 << index)) && cb->buffer) {

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