| /external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| H A D | nv98_video_vp.c | 28 struct nouveau_bo *inter_bo, unsigned slice_size)
50 for (i = 0; i < comm->byte_ofs + slice_size; i += 0x10) {
75 uint32_t slice_size, bucket_size, ring_size, i; local
92 nouveau_vp3_inter_sizes(dec, desc.h264->slice_count, &slice_size, &bucket_size, &ring_size);
95 nouveau_vp3_inter_sizes(dec, 1, &slice_size, &bucket_size, &ring_size);
137 PUSH_DATA (push, inter_addr + slice_size + bucket_size); // 718 inter_data_ofs
144 PUSH_DATA (push, inter_addr + slice_size); // 720 bucket_ofs
187 dump_comm_vp(dec, dec->comm, comm_seq, inter_bo, slice_size << 8);
191 dump_comm_vp(dec, dec->comm, comm_seq, inter_bo, slice_size << 8);
27 dump_comm_vp(struct nouveau_vp3_decoder *dec, struct comm *comm, u32 comm_seq, struct nouveau_bo *inter_bo, unsigned slice_size) argument
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| H A D | nv98_video_bsp.c | 45 uint32_t slice_size, bucket_size, ring_size, bsp_size; local
136 nouveau_vp3_inter_sizes(dec, 1, &slice_size, &bucket_size, &ring_size);
140 PUSH_DATA (push, inter_addr + slice_size + bucket_size); // 408 interdata addr
148 nouveau_vp3_inter_sizes(dec, desc.h264->slice_count, &slice_size, &bucket_size, &ring_size);
152 PUSH_DATA (push, slice_size << 8); // 408 interparm size?
153 PUSH_DATA (push, inter_addr + slice_size + bucket_size); // 40c interdata addr
155 PUSH_DATA (push, inter_addr + slice_size); // 414 bucket?
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| /external/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| H A D | nvc0_video_vp.c | 28 struct nouveau_bo *inter_bo, unsigned slice_size)
50 for (i = 0; i < comm->byte_ofs + slice_size; i += 0x10) {
75 uint32_t slice_size, bucket_size, ring_size, i; local
92 nouveau_vp3_inter_sizes(dec, desc.h264->slice_count, &slice_size, &bucket_size, &ring_size);
95 nouveau_vp3_inter_sizes(dec, 1, &slice_size, &bucket_size, &ring_size);
137 PUSH_DATA (push, inter_addr + slice_size + bucket_size); // 718 inter_data_ofs
144 PUSH_DATA (push, inter_addr + slice_size); // 720 bucket_ofs
187 dump_comm_vp(dec, dec->comm, comm_seq, inter_bo, slice_size << 8);
191 dump_comm_vp(dec, dec->comm, comm_seq, inter_bo, slice_size << 8);
27 dump_comm_vp(struct nouveau_vp3_decoder *dec, struct comm *comm, u32 comm_seq, struct nouveau_bo *inter_bo, unsigned slice_size) argument
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| H A D | nvc0_video_bsp.c | 142 uint32_t slice_size, bucket_size, ring_size; local
188 nouveau_vp3_inter_sizes(dec, 1, &slice_size, &bucket_size, &ring_size);
192 PUSH_DATA (push, inter_addr + slice_size + bucket_size); // 408 interdata addr
197 nouveau_vp3_inter_sizes(dec, desc.h264->slice_count, &slice_size, &bucket_size, &ring_size);
201 PUSH_DATA (push, slice_size << 8); // 408 interparm size?
202 PUSH_DATA (push, inter_addr + slice_size + bucket_size); // 40c interdata addr
204 PUSH_DATA (push, inter_addr + slice_size); // 414 bucket?
|
| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_surface.c | 74 level_drm->slice_size = level_ws->slice_size;
86 level_ws->slice_size = level_drm->slice_size;
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| H A D | radeon_drm_bo.c | 1292 unsigned slice_size,
1332 whandle->offset += slice_size * whandle->layer;
1290 radeon_winsys_bo_get_handle(struct pb_buffer *buffer, unsigned stride, unsigned offset, unsigned slice_size, struct winsys_handle *whandle) argument
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| /external/mesa3d/src/gallium/drivers/nouveau/ |
| H A D | nouveau_vp3_video.h | 192 uint32_t *slice_size, uint32_t *bucket_size,
195 *slice_size = (SLICE_SIZE * slice_count)>>8;
200 *ring_size = (dec->inter_bo[0]->size >> 8) - *bucket_size - *slice_size;
191 nouveau_vp3_inter_sizes(struct nouveau_vp3_decoder *dec, uint32_t slice_count, uint32_t *slice_size, uint32_t *bucket_size, uint32_t *ring_size) argument
|
| /external/libdrm/radeon/ |
| H A D | radeon_surface.h | 71 uint64_t slice_size; member in struct:radeon_surface_level
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| H A D | radeon_surface.c | 195 surflevel->slice_size = (uint64_t)surflevel->pitch_bytes * surflevel->nblk_y;
197 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
609 surflevel->slice_size = (uint64_t)mtile_ps * mtileb * slice_pt;
611 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
1466 surflevel->slice_size = ALIGN((uint64_t)surflevel->pitch_bytes * surflevel->nblk_y,
1469 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
1515 surflevel->slice_size = (uint64_t)mtile_ps * mtileb * slice_pt;
1517 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| H A D | si_dma.c | 180 addr += rlinear->surface.level[linear_lvl].slice_size * linear_z;
304 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
307 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
310 rsrc->surface.level[src_level].slice_size);
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| H A D | cik_sdma.c | 166 uint64_t dst_slice_pitch = rdst->surface.level[dst_level].slice_size / bpp;
167 uint64_t src_slice_pitch = rsrc->surface.level[src_level].slice_size / bpp;
|
| /external/mesa3d/src/gallium/drivers/svga/include/ |
| H A D | svga3d_surfacedefs.h | 1023 uint32 slice_size, total_size; local
1038 slice_size = clamped_umul32(image_blocks.height, pitch);
1039 total_size = clamped_umul32(slice_size, image_blocks.depth);
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | radeon_winsys.h | 289 uint64_t slice_size; member in struct:radeon_surf_level
501 unsigned slice_size,
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| H A D | r600_texture.c | 184 box->z * rtex->surface.level[level].slice_size +
271 surface->level[0].slice_size = pitch_in_bytes_override * surface->level[0].nblk_y;
557 rtex->surface.level[0].slice_size,
950 fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
954 rtex->surface.level[i].slice_size,
968 "slice_size=%"PRIu64", npix_x=%u, "
972 rtex->surface.stencil_level[i].slice_size,
1554 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
1576 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1588 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
[all...] |
| H A D | radeon_uvd.c | 1321 layer * surface->level[0].slice_size;
|
| /external/mesa3d/src/amd/vulkan/ |
| H A D | radv_image.c | 745 image->surface.level[0].slice_size = create_info->stride * image->surface.level[0].nblk_y;
957 pLayout->offset = image->surface.level[level].offset + image->surface.level[level].slice_size * layer;
959 pLayout->arrayPitch = image->surface.level[level].slice_size;
960 pLayout->depthPitch = image->surface.level[level].slice_size;
961 pLayout->size = image->surface.level[level].slice_size;
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| H A D | radv_radeon_winsys.h | 158 uint64_t slice_size; member in struct:radeon_surf_level
|
| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| H A D | radv_amdgpu_surface.c | 204 surf_level->slice_size = AddrSurfInfoOut->sliceSize;
|
| /external/mesa3d/src/gallium/drivers/ilo/core/ |
| H A D | ilo_image.c | 237 const uint64_t slice_size = info->width * info->height * local
241 const uint64_t estimated_size = slice_size * slice_count;
|
| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| H A D | amdgpu_bo.c | 872 unsigned slice_size,
906 whandle->offset += slice_size * whandle->layer;
870 amdgpu_bo_get_handle(struct pb_buffer *buffer, unsigned stride, unsigned offset, unsigned slice_size, struct winsys_handle *whandle) argument
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| H A D | amdgpu_surface.c | 193 surf_level->slice_size = AddrSurfInfoOut->sliceSize;
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| /external/mesa3d/src/gallium/drivers/r600/ |
| H A D | evergreen_state.c | 3391 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3416 addr += rsrc->surface.level[src_level].slice_size * src_z;
3533 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3536 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
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| H A D | r600_state.c | 2852 addr += rdst->surface.level[dst_level].slice_size * dst_z;
2871 addr += rsrc->surface.level[src_level].slice_size * src_z;
2976 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
2979 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
|