Searched refs:v4i16 (Results 1 - 25 of 25) sorted by relevance

/external/clang/test/CodeGen/
H A Dppc64-vector.c5 typedef short v4i16 __attribute__((vector_size (8))); typedef
25 v4i16 test_v4i16(v4i16 x)
H A Dsystemz-abi-vector.c21 typedef __attribute__((vector_size(8))) short v4i16; typedef
74 v4i16 pass_v4i16(v4i16 arg) { return arg; }
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
H A DValueTypes.h60 v4i16 = 18, // 4 x i16 enumerator in enum:llvm::MVT::SimpleValueType
196 case v4i16:
227 case v4i16:
264 case v4i16:
347 if (NumElements == 4) return MVT::v4i16;
434 case 4: return MVT::v4i16;
488 return (V == MVT::v8i8 || V==MVT::v4i16 || V==MVT::v2i32 ||
/external/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp105 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
106 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
110 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
113 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
114 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
142 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
143 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
157 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
158 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
396 {ISD::VECTOR_SHUFFLE, MVT::v4i16,
[all...]
H A DARMISelLowering.cpp467 addDRTypeForNEON(MVT::v4i16);
557 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
559 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
567 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
568 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
569 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
570 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
580 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
590 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
600 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custo
[all...]
H A DARMISelDAGToDAG.cpp1830 case MVT::v4i16: OpcodeIndex = 1; break;
1970 case MVT::v4i16: OpcodeIndex = 1; break;
2134 case MVT::v4i16: OpcodeIndex = 1; break;
2248 case MVT::v4i16: OpcodeIndex = 1; break;
3069 case MVT::v4i16: Opc = ARM::VZIPd16; break;
3090 case MVT::v4i16: Opc = ARM::VUZPd16; break;
3111 case MVT::v4i16: Opc = ARM::VTRNd16; break;
/external/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp594 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
627 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
628 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
635 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 },
658 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
659 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
669 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 },
679 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 },
680 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 },
692 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16,
[all...]
H A DX86ISelLowering.cpp795 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
801 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
836 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
849 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
916 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
923 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1070 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1077 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1200 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1209 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Lega
[all...]
/external/llvm/include/llvm/CodeGen/
H A DMachineValueType.h80 v4i16 = 32, // 4 x i16
241 return (SimpleTy == MVT::v8i8 || SimpleTy == MVT::v4i16 ||
336 case v4i16:
405 case v4i16:
472 case v4i16:
616 if (NumElements == 4) return MVT::v4i16;
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp484 case MVT::v4i16:
2750 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2777 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2804 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2831 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2858 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2885 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2912 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2939 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
2966 } else if (VT == MVT::v4i16 || V
[all...]
H A DAArch64TargetTransformInfo.cpp191 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
197 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
198 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
232 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
234 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
271 // Complex, from v4f32: legal type is v4i16, 1 narrowing => ~2
272 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
274 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
H A DAArch64ISelLowering.cpp87 addDRTypeForNEON(MVT::v4i16);
561 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
562 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
583 setOperationAction(ISD::CTTZ, MVT::v4i16, Expand);
785 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
2102 return MVT::v4i16;
5816 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5825 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6016 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
6025 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
[all...]
/external/swiftshader/third_party/LLVM/lib/VMCore/
H A DValueTypes.cpp126 case MVT::v4i16: return "v4i16";
173 case MVT::v4i16: return VectorType::get(Type::getInt16Ty(Context), 4);
/external/llvm/lib/IR/
H A DValueTypes.cpp164 case MVT::v4i16: return "v4i16";
242 case MVT::v4i16: return VectorType::get(Type::getInt16Ty(Context), 4);
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp242 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
409 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
1224 if (VT.getSimpleVT() == MVT::v4i16)
1336 if (VT == MVT::v4i16) {
1745 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1920 // Custom lower v4i16 load only. Let v4i16 store to be
1927 setOperationAction(ISD::LOAD, MVT::v4i16, Custom);
1928 setOperationAction(ISD::STORE, MVT::v4i16, Promote);
1929 AddPromotedToType(ISD::LOAD, MVT::v4i16, MV
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1573 case MVT::v4i16: OpcodeIndex = 1; break;
1701 case MVT::v4i16: OpcodeIndex = 1; break;
1855 case MVT::v4i16: OpcodeIndex = 1; break;
1967 case MVT::v4i16: OpcodeIndex = 1; break;
2650 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2669 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2688 case MVT::v4i16: Opc = ARM::VTRNd16; break;
H A DARMISelLowering.cpp447 addDRTypeForNEON(MVT::v4i16);
494 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
496 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
502 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
503 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
782 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
3037 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3590 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
4720 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
4757 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N
[all...]
/external/llvm/utils/TableGen/
H A DCodeGenTarget.cpp92 case MVT::v4i16: return "MVT::v4i16";
/external/swiftshader/third_party/LLVM/utils/TableGen/
H A DCodeGenTarget.cpp75 case MVT::v4i16: return "MVT::v4i16";
/external/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp136 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
137 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
138 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
187 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
H A DR600ISelLowering.cpp156 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
H A DSIISelLowering.cpp123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp66 case MVT::v4i16:
1934 case MVT::v4i16:
4308 case MVT::v4i16:
/external/llvm/lib/Target/X86/InstPrinter/
H A DX86InstComments.cpp618 DecodePSHUFMask(MVT::v4i16,
/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86ISelLowering.cpp760 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
764 setOperationAction(ISD::AND, MVT::v4i16, Expand);
768 setOperationAction(ISD::OR, MVT::v4i16, Expand);
772 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
776 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
781 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
785 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);

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