Searched refs:v4i64 (Results 1 - 23 of 23) sorted by relevance

/external/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle.
149 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
159 { ISD::SHL, MVT::v4i64, 1 },
160 { ISD::SRL, MVT::v4i64, 1 },
200 { ISD::SHL, MVT::v4i64, 2 },
201 { ISD::SRL, MVT::v4i64, 4 },
202 { ISD::SRA, MVT::v4i64, 4 },
221 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence.
227 { ISD::SDIV, MVT::v4i64, 4*20 },
231 { ISD::UDIV, MVT::v4i64,
[all...]
H A DX86ISelLowering.cpp934 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
942 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
953 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
991 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
994 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
997 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1000 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1003 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1011 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
1016 // ISD::CTLZ v8i32/v4i64
[all...]
H A DX86FastISel.cpp447 case MVT::v4i64:
595 case MVT::v4i64:
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
H A DValueTypes.h68 v4i64 = 26, // 4 x i64 enumerator in enum:llvm::MVT::SimpleValueType
204 case v4i64:
229 case v4i64:
281 case v4i64:
359 if (NumElements == 4) return MVT::v4i64;
505 V == MVT::v16i16 || V == MVT::v8i32 || V == MVT::v4i64);
/external/llvm/include/llvm/CodeGen/
H A DMachineValueType.h97 v4i64 = 47, // 4 x i64
259 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64);
351 case v4i64:
407 case v4i64:
493 case v4i64:
635 if (NumElements == 4) return MVT::v4i64;
/external/swiftshader/third_party/LLVM/lib/VMCore/
H A DValueTypes.cpp134 case MVT::v4i64: return "v4i64";
181 case MVT::v4i64: return VectorType::get(Type::getInt64Ty(Context), 4);
/external/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp192 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
197 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
198 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
199 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
200 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
449 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4 * AmortizationCost },
H A DAArch64ISelLowering.cpp7730 ResTy = FloatBits == 32 ? MVT::v4i32 : MVT::v4i64;
7734 if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps())
7737 assert((ResTy != MVT::v4i64 || DCI.isBeforeLegalizeOps()) &&
/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86GenDAGISel.inc5737 /*12606*/ OPC_CheckChild1Type, MVT::v4i64,
5748 // Src: (st VR256:v4i64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore256>> - Complexity = 22
5749 // Dst: (VMOVAPSYmr addr:iPTR:$dst, VR256:v4i64:$src)
5756 // Src: (st VR256:v4i64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 22
5757 // Dst: (VMOVUPSYmr addr:iPTR:$dst, VR256:v4i64:$src)
6196 /*13585*/ OPC_CheckType, MVT::v4i64,
6203 1/*#VTs*/, MVT::v4i64, 3/*#Ops*/, 1, 2, 3,
6204 // Src: (X86vzmovl:v4i64 (insert_subvector:v4i64 (undef:v4i64), (scalar_to_vecto
[all...]
H A DX86GenFastISel.inc1174 if (RetVT.SimpleTy != MVT::v4i64)
1193 case MVT::v4i64: return FastEmit_X86ISD_MOVDDUP_MVT_v4i64_r(RetVT, Op0, Op0IsKill);
1571 if (RetVT.SimpleTy != MVT::v4i64)
1586 case MVT::v4i64: return FastEmit_ISD_AND_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2068 if (RetVT.SimpleTy != MVT::v4i64)
2083 case MVT::v4i64: return FastEmit_ISD_OR_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2298 if (RetVT.SimpleTy != MVT::v4i64)
2313 case MVT::v4i64: return FastEmit_ISD_XOR_MVT_v4i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2333 if (RetVT.SimpleTy != MVT::v4i64)
2344 case MVT::v4i64
[all...]
H A DX86ISelLowering.cpp979 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
984 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1005 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1011 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1016 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1027 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1030 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1034 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1038 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1043 setOperationAction(ISD::SUB, MVT::v4i64, Custo
[all...]
H A DX86GenRegisterInfo.inc2720 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::v8f32, MVT::v4f64, MVT::Other
/external/llvm/lib/IR/
H A DValueTypes.cpp179 case MVT::v4i64: return "v4i64";
257 case MVT::v4i64: return VectorType::get(Type::getInt64Ty(Context), 4);
/external/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp109 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
113 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
114 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
301 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
H A DARMISelDAGToDAG.cpp2012 SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2018 SrcReg = SDValue(createQRegPairNode(MVT::v4i64, Q0, Q1), 0);
2173 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
2180 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2316 RegSeq = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
H A DARMISelLowering.cpp1102 case MVT::v4i64:
1261 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1262 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1265 if (VT == MVT::v4i64)
/external/swiftshader/third_party/LLVM/lib/Target/X86/Utils/
H A DX86ShuffleDecode.cpp239 // instruction comments purpose, assume the 256-bit vector is v4i64.
240 return DecodeVPERM2F128Mask(MVT::v4i64, Imm, ShuffleMask);
/external/llvm/utils/TableGen/
H A DCodeGenTarget.cpp107 case MVT::v4i64: return "MVT::v4i64";
/external/swiftshader/third_party/LLVM/utils/TableGen/
H A DCodeGenTarget.cpp83 case MVT::v4i64: return "MVT::v4i64";
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1742 SrcReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1748 SrcReg = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0);
1894 SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1901 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
2030 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
H A DARMISelLowering.cpp797 case MVT::v4i64:
953 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
954 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
957 if (VT == MVT::v4i64)
/external/llvm/lib/Target/X86/InstPrinter/
H A DX86InstComments.cpp841 // For instruction comments purpose, assume the 256-bit vector is v4i64.
843 DecodeVPERM2X128Mask(MVT::v4i64,
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp191 if (LocVT == MVT::v4i64 || LocVT == MVT::v8i32 || LocVT == MVT::v16i16 ||

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