1#ifndef __NVIF_CLASS_H__ 2#define __NVIF_CLASS_H__ 3 4/******************************************************************************* 5 * class identifiers 6 ******************************************************************************/ 7 8/* the below match nvidia-assigned (either in hw, or sw) class numbers */ 9#define NV_DEVICE 0x00000080 10 11#define NV_DMA_FROM_MEMORY 0x00000002 12#define NV_DMA_TO_MEMORY 0x00000003 13#define NV_DMA_IN_MEMORY 0x0000003d 14 15#define FERMI_TWOD_A 0x0000902d 16 17#define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x0000903d 18 19#define KEPLER_INLINE_TO_MEMORY_A 0x0000a040 20#define KEPLER_INLINE_TO_MEMORY_B 0x0000a140 21 22#define NV04_DISP 0x00000046 23 24#define NV03_CHANNEL_DMA 0x0000006b 25#define NV10_CHANNEL_DMA 0x0000006e 26#define NV17_CHANNEL_DMA 0x0000176e 27#define NV40_CHANNEL_DMA 0x0000406e 28#define NV50_CHANNEL_DMA 0x0000506e 29#define G82_CHANNEL_DMA 0x0000826e 30 31#define NV50_CHANNEL_GPFIFO 0x0000506f 32#define G82_CHANNEL_GPFIFO 0x0000826f 33#define FERMI_CHANNEL_GPFIFO 0x0000906f 34#define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f 35#define MAXWELL_CHANNEL_GPFIFO_A 0x0000b06f 36 37#define NV50_DISP 0x00005070 38#define G82_DISP 0x00008270 39#define GT200_DISP 0x00008370 40#define GT214_DISP 0x00008570 41#define GT206_DISP 0x00008870 42#define GF110_DISP 0x00009070 43#define GK104_DISP 0x00009170 44#define GK110_DISP 0x00009270 45#define GM107_DISP 0x00009470 46#define GM204_DISP 0x00009570 47 48#define NV50_DISP_CURSOR 0x0000507a 49#define G82_DISP_CURSOR 0x0000827a 50#define GT214_DISP_CURSOR 0x0000857a 51#define GF110_DISP_CURSOR 0x0000907a 52#define GK104_DISP_CURSOR 0x0000917a 53 54#define NV50_DISP_OVERLAY 0x0000507b 55#define G82_DISP_OVERLAY 0x0000827b 56#define GT214_DISP_OVERLAY 0x0000857b 57#define GF110_DISP_OVERLAY 0x0000907b 58#define GK104_DISP_OVERLAY 0x0000917b 59 60#define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c 61#define G82_DISP_BASE_CHANNEL_DMA 0x0000827c 62#define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c 63#define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c 64#define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c 65#define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c 66#define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c 67 68#define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d 69#define G82_DISP_CORE_CHANNEL_DMA 0x0000827d 70#define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d 71#define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d 72#define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d 73#define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d 74#define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d 75#define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d 76#define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d 77#define GM204_DISP_CORE_CHANNEL_DMA 0x0000957d 78 79#define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e 80#define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e 81#define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e 82#define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e 83#define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e 84#define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e 85 86#define FERMI_A 0x00009097 87#define FERMI_B 0x00009197 88#define FERMI_C 0x00009297 89 90#define KEPLER_A 0x0000a097 91#define KEPLER_B 0x0000a197 92#define KEPLER_C 0x0000a297 93 94#define MAXWELL_A 0x0000b097 95#define MAXWELL_B 0x0000b197 96 97#define FERMI_COMPUTE_A 0x000090c0 98#define FERMI_COMPUTE_B 0x000091c0 99 100#define KEPLER_COMPUTE_A 0x0000a0c0 101#define KEPLER_COMPUTE_B 0x0000a1c0 102 103#define MAXWELL_COMPUTE_A 0x0000b0c0 104#define MAXWELL_COMPUTE_B 0x0000b1c0 105 106#define MAXWELL_DMA_COPY_A 0x0000b0b5 107 108/******************************************************************************* 109 * client 110 ******************************************************************************/ 111 112#define NV_CLIENT_DEVLIST 0x00 113 114struct nv_client_devlist_v0 { 115 __u8 version; 116 __u8 count; 117 __u8 pad02[6]; 118 __u64 device[]; 119}; 120 121 122/******************************************************************************* 123 * device 124 ******************************************************************************/ 125 126struct nv_device_v0 { 127 __u8 version; 128 __u8 pad01[7]; 129 __u64 device; /* device identifier, ~0 for client default */ 130#define NV_DEVICE_V0_DISABLE_IDENTIFY 0x0000000000000001ULL 131#define NV_DEVICE_V0_DISABLE_MMIO 0x0000000000000002ULL 132#define NV_DEVICE_V0_DISABLE_VBIOS 0x0000000000000004ULL 133#define NV_DEVICE_V0_DISABLE_CORE 0x0000000000000008ULL 134#define NV_DEVICE_V0_DISABLE_DISP 0x0000000000010000ULL 135#define NV_DEVICE_V0_DISABLE_FIFO 0x0000000000020000ULL 136#define NV_DEVICE_V0_DISABLE_GR 0x0000000100000000ULL 137#define NV_DEVICE_V0_DISABLE_MPEG 0x0000000200000000ULL 138#define NV_DEVICE_V0_DISABLE_ME 0x0000000400000000ULL 139#define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL 140#define NV_DEVICE_V0_DISABLE_CIPHER 0x0000001000000000ULL 141#define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL 142#define NV_DEVICE_V0_DISABLE_MSPPP 0x0000004000000000ULL 143#define NV_DEVICE_V0_DISABLE_CE0 0x0000008000000000ULL 144#define NV_DEVICE_V0_DISABLE_CE1 0x0000010000000000ULL 145#define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL 146#define NV_DEVICE_V0_DISABLE_MSENC 0x0000040000000000ULL 147#define NV_DEVICE_V0_DISABLE_CE2 0x0000080000000000ULL 148#define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL 149#define NV_DEVICE_V0_DISABLE_SEC 0x0000200000000000ULL 150#define NV_DEVICE_V0_DISABLE_MSPDEC 0x0000400000000000ULL 151 __u64 disable; /* disable particular subsystems */ 152 __u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */ 153}; 154 155#define NV_DEVICE_V0_INFO 0x00 156#define NV_DEVICE_V0_ZCULL_INFO 0x01 157 158struct nv_device_info_v0 { 159 __u8 version; 160#define NV_DEVICE_INFO_V0_IGP 0x00 161#define NV_DEVICE_INFO_V0_PCI 0x01 162#define NV_DEVICE_INFO_V0_AGP 0x02 163#define NV_DEVICE_INFO_V0_PCIE 0x03 164#define NV_DEVICE_INFO_V0_SOC 0x04 165 __u8 platform; 166 __u16 chipset; /* from NV_PMC_BOOT_0 */ 167 __u8 revision; /* from NV_PMC_BOOT_0 */ 168#define NV_DEVICE_INFO_V0_TNT 0x01 169#define NV_DEVICE_INFO_V0_CELSIUS 0x02 170#define NV_DEVICE_INFO_V0_KELVIN 0x03 171#define NV_DEVICE_INFO_V0_RANKINE 0x04 172#define NV_DEVICE_INFO_V0_CURIE 0x05 173#define NV_DEVICE_INFO_V0_TESLA 0x06 174#define NV_DEVICE_INFO_V0_FERMI 0x07 175#define NV_DEVICE_INFO_V0_KEPLER 0x08 176#define NV_DEVICE_INFO_V0_MAXWELL 0x09 177 __u8 family; 178 __u8 pad06[2]; 179 __u64 ram_size; 180 __u64 ram_user; 181}; 182 183struct nv_device_zcull_info_v0 { 184 __u8 version; 185 __u8 pad03[3]; 186 __u32 image_size; 187 __u32 width_align_pixels; 188 __u32 height_align_pixels; 189 __u32 pixel_squares_by_aliquots; 190 __u32 aliquot_total; 191 __u32 region_byte_multiplier; 192 __u32 region_header_size; 193 __u32 subregion_header_size; 194 __u32 subregion_width_align_pixels; 195 __u32 subregion_height_align_pixels; 196 __u32 subregion_count; 197}; 198 199/******************************************************************************* 200 * context dma 201 ******************************************************************************/ 202 203struct nv_dma_v0 { 204 __u8 version; 205#define NV_DMA_V0_TARGET_VM 0x00 206#define NV_DMA_V0_TARGET_VRAM 0x01 207#define NV_DMA_V0_TARGET_PCI 0x02 208#define NV_DMA_V0_TARGET_PCI_US 0x03 209#define NV_DMA_V0_TARGET_AGP 0x04 210 __u8 target; 211#define NV_DMA_V0_ACCESS_VM 0x00 212#define NV_DMA_V0_ACCESS_RD 0x01 213#define NV_DMA_V0_ACCESS_WR 0x02 214#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR) 215 __u8 access; 216 __u8 pad03[5]; 217 __u64 start; 218 __u64 limit; 219 /* ... chipset-specific class data */ 220}; 221 222struct nv50_dma_v0 { 223 __u8 version; 224#define NV50_DMA_V0_PRIV_VM 0x00 225#define NV50_DMA_V0_PRIV_US 0x01 226#define NV50_DMA_V0_PRIV__S 0x02 227 __u8 priv; 228#define NV50_DMA_V0_PART_VM 0x00 229#define NV50_DMA_V0_PART_256 0x01 230#define NV50_DMA_V0_PART_1KB 0x02 231 __u8 part; 232#define NV50_DMA_V0_COMP_NONE 0x00 233#define NV50_DMA_V0_COMP_1 0x01 234#define NV50_DMA_V0_COMP_2 0x02 235#define NV50_DMA_V0_COMP_VM 0x03 236 __u8 comp; 237#define NV50_DMA_V0_KIND_PITCH 0x00 238#define NV50_DMA_V0_KIND_VM 0x7f 239 __u8 kind; 240 __u8 pad05[3]; 241}; 242 243struct gf100_dma_v0 { 244 __u8 version; 245#define GF100_DMA_V0_PRIV_VM 0x00 246#define GF100_DMA_V0_PRIV_US 0x01 247#define GF100_DMA_V0_PRIV__S 0x02 248 __u8 priv; 249#define GF100_DMA_V0_KIND_PITCH 0x00 250#define GF100_DMA_V0_KIND_VM 0xff 251 __u8 kind; 252 __u8 pad03[5]; 253}; 254 255struct gf110_dma_v0 { 256 __u8 version; 257#define GF110_DMA_V0_PAGE_LP 0x00 258#define GF110_DMA_V0_PAGE_SP 0x01 259 __u8 page; 260#define GF110_DMA_V0_KIND_PITCH 0x00 261#define GF110_DMA_V0_KIND_VM 0xff 262 __u8 kind; 263 __u8 pad03[5]; 264}; 265 266 267/******************************************************************************* 268 * perfmon 269 ******************************************************************************/ 270 271struct nvif_perfctr_v0 { 272 __u8 version; 273 __u8 pad01[1]; 274 __u16 logic_op; 275 __u8 pad04[4]; 276 char name[4][64]; 277}; 278 279#define NVIF_PERFCTR_V0_QUERY 0x00 280#define NVIF_PERFCTR_V0_SAMPLE 0x01 281#define NVIF_PERFCTR_V0_READ 0x02 282 283struct nvif_perfctr_query_v0 { 284 __u8 version; 285 __u8 pad01[3]; 286 __u32 iter; 287 char name[64]; 288}; 289 290struct nvif_perfctr_sample { 291}; 292 293struct nvif_perfctr_read_v0 { 294 __u8 version; 295 __u8 pad01[7]; 296 __u32 ctr; 297 __u32 clk; 298}; 299 300 301/******************************************************************************* 302 * device control 303 ******************************************************************************/ 304 305#define NVIF_CONTROL_PSTATE_INFO 0x00 306#define NVIF_CONTROL_PSTATE_ATTR 0x01 307#define NVIF_CONTROL_PSTATE_USER 0x02 308 309struct nvif_ustate { 310 __s8 min; 311 __s8 max; 312}; 313 314struct nvif_control_pstate_info_v0 { 315 __u8 version; 316 __u8 count; /* out: number of power states */ 317#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1) 318#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2) 319 struct { 320 struct nvif_ustate dc; // pwrsrc == 0 321 struct nvif_ustate ac; // pwrsrc == 1 322 } ustate; /* out: target pstate index */ 323 __s8 pwrsrc; /* out: current power source */ 324#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1) 325#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2) 326 __s8 pstate; /* out: current pstate index */ 327 __u8 pad06[2]; 328}; 329 330struct nvif_control_pstate_attr_v0 { 331 __u8 version; 332#define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1) 333 __s8 state; /* in: index of pstate to query 334 * out: pstate identifier 335 */ 336 __u8 index; /* in: index of attribute to query 337 * out: index of next attribute, or 0 if no more 338 */ 339 __u8 pad03[5]; 340 __u32 min; 341 __u32 max; 342 char name[32]; 343 char unit[16]; 344}; 345 346struct nvif_control_pstate_user_v0 { 347 __u8 version; 348#define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1) 349#define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2) 350 struct nvif_ustate ustate; /* in: pstate identifier */ 351 __s8 pwrsrc; /* in: target power source */ 352 __u8 pad03[5]; 353}; 354 355 356/******************************************************************************* 357 * DMA FIFO channels 358 ******************************************************************************/ 359 360struct nv03_channel_dma_v0 { 361 __u8 version; 362 __u8 chid; 363 __u8 pad02[2]; 364 __u32 pushbuf; 365 __u64 offset; 366}; 367 368#define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 369 370/******************************************************************************* 371 * GPFIFO channels 372 ******************************************************************************/ 373 374struct nv50_channel_gpfifo_v0 { 375 __u8 version; 376 __u8 chid; 377 __u8 pad01[6]; 378 __u32 pushbuf; 379 __u32 ilength; 380 __u64 ioffset; 381}; 382 383struct kepler_channel_gpfifo_a_v0 { 384 __u8 version; 385#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01 386#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC 0x02 387#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP 0x04 388#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08 389#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10 390#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20 391#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40 392 __u8 engine; 393 __u16 chid; 394 __u8 pad04[4]; 395 __u32 pushbuf; 396 __u32 ilength; 397 __u64 ioffset; 398}; 399 400#define CHANNEL_GPFIFO_ERROR_NOTIFIER_EEVENT 0x01 401 402/******************************************************************************* 403 * legacy display 404 ******************************************************************************/ 405 406#define NV04_DISP_NTFY_VBLANK 0x00 407#define NV04_DISP_NTFY_CONN 0x01 408 409struct nv04_disp_mthd_v0 { 410 __u8 version; 411#define NV04_DISP_SCANOUTPOS 0x00 412 __u8 method; 413 __u8 head; 414 __u8 pad03[5]; 415}; 416 417struct nv04_disp_scanoutpos_v0 { 418 __u8 version; 419 __u8 pad01[7]; 420 __s64 time[2]; 421 __u16 vblanks; 422 __u16 vblanke; 423 __u16 vtotal; 424 __u16 vline; 425 __u16 hblanks; 426 __u16 hblanke; 427 __u16 htotal; 428 __u16 hline; 429}; 430 431/******************************************************************************* 432 * display 433 ******************************************************************************/ 434 435#define NV50_DISP_MTHD 0x00 436 437struct nv50_disp_mthd_v0 { 438 __u8 version; 439#define NV50_DISP_SCANOUTPOS 0x00 440 __u8 method; 441 __u8 head; 442 __u8 pad03[5]; 443}; 444 445struct nv50_disp_mthd_v1 { 446 __u8 version; 447#define NV50_DISP_MTHD_V1_DAC_PWR 0x10 448#define NV50_DISP_MTHD_V1_DAC_LOAD 0x11 449#define NV50_DISP_MTHD_V1_SOR_PWR 0x20 450#define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21 451#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22 452#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23 453#define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24 454#define NV50_DISP_MTHD_V1_PIOR_PWR 0x30 455 __u8 method; 456 __u16 hasht; 457 __u16 hashm; 458 __u8 pad06[2]; 459}; 460 461struct nv50_disp_dac_pwr_v0 { 462 __u8 version; 463 __u8 state; 464 __u8 data; 465 __u8 vsync; 466 __u8 hsync; 467 __u8 pad05[3]; 468}; 469 470struct nv50_disp_dac_load_v0 { 471 __u8 version; 472 __u8 load; 473 __u8 pad02[2]; 474 __u32 data; 475}; 476 477struct nv50_disp_sor_pwr_v0 { 478 __u8 version; 479 __u8 state; 480 __u8 pad02[6]; 481}; 482 483struct nv50_disp_sor_hda_eld_v0 { 484 __u8 version; 485 __u8 pad01[7]; 486 __u8 data[]; 487}; 488 489struct nv50_disp_sor_hdmi_pwr_v0 { 490 __u8 version; 491 __u8 state; 492 __u8 max_ac_packet; 493 __u8 rekey; 494 __u8 pad04[4]; 495}; 496 497struct nv50_disp_sor_lvds_script_v0 { 498 __u8 version; 499 __u8 pad01[1]; 500 __u16 script; 501 __u8 pad04[4]; 502}; 503 504struct nv50_disp_sor_dp_pwr_v0 { 505 __u8 version; 506 __u8 state; 507 __u8 pad02[6]; 508}; 509 510struct nv50_disp_pior_pwr_v0 { 511 __u8 version; 512 __u8 state; 513 __u8 type; 514 __u8 pad03[5]; 515}; 516 517/* core */ 518struct nv50_disp_core_channel_dma_v0 { 519 __u8 version; 520 __u8 pad01[3]; 521 __u32 pushbuf; 522}; 523 524#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 525 526/* cursor immediate */ 527struct nv50_disp_cursor_v0 { 528 __u8 version; 529 __u8 head; 530 __u8 pad02[6]; 531}; 532 533#define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00 534 535/* base */ 536struct nv50_disp_base_channel_dma_v0 { 537 __u8 version; 538 __u8 pad01[2]; 539 __u8 head; 540 __u32 pushbuf; 541}; 542 543#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 544 545/* overlay */ 546struct nv50_disp_overlay_channel_dma_v0 { 547 __u8 version; 548 __u8 pad01[2]; 549 __u8 head; 550 __u32 pushbuf; 551}; 552 553#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 554 555/* overlay immediate */ 556struct nv50_disp_overlay_v0 { 557 __u8 version; 558 __u8 head; 559 __u8 pad02[6]; 560}; 561 562#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00 563 564/******************************************************************************* 565 * fermi 566 ******************************************************************************/ 567 568#define FERMI_A_ZBC_COLOR 0x00 569#define FERMI_A_ZBC_DEPTH 0x01 570#define FERMI_A_ZCULL_BIND 0x02 571#define FERMI_A_ZBC_QUERY_COLOR 0x03 572#define FERMI_A_ZBC_QUERY_DEPTH 0x04 573#define FERMI_A_ZBC_QUERY_TABLE_SIZE 0x05 574 575struct fermi_a_zbc_color_v0 { 576 __u8 version; 577#define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01 578#define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE 0x02 579#define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32 0x04 580#define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16 0x08 581#define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16 0x0c 582#define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16 0x10 583#define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16 0x14 584#define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16 0x16 585#define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8 0x18 586#define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8 0x1c 587#define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10 0x20 588#define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10 0x24 589#define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8 0x28 590#define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8 0x2c 591#define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8 0x30 592#define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8 0x34 593#define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8 0x38 594#define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10 0x3c 595#define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11 0x40 596 __u8 format; 597 __u8 index; 598 __u8 pad03[5]; 599 __u32 ds[4]; 600 __u32 l2[4]; 601}; 602 603struct fermi_a_zbc_query_v0 { 604 __u8 version; 605 __u8 pad03[3]; 606 __u32 ds[4]; 607 __u32 l2[4]; 608 __u32 format; 609 __u32 index; 610 __u32 table_size; 611}; 612 613struct fermi_a_zbc_depth_v0 { 614 __u8 version; 615#define FERMI_A_ZBC_DEPTH_V0_FMT_FP32 0x01 616 __u8 format; 617 __u8 index; 618 __u8 pad03[5]; 619 __u32 ds; 620 __u32 l2; 621}; 622 623struct fermi_a_zcull_bind_v0 { 624 __u8 version; 625 __u8 pad03[3]; 626#define FERMI_A_ZCULL_BIND_MODE_GLOBAL 0x00 627#define FERMI_A_ZCULL_BIND_MODE_NO_CTXSW 0x01 628#define FERMI_A_ZCULL_BIND_MODE_SEPARATE_BUFFER 0x02 629 __u32 mode; 630 __u64 gpu_va; 631}; 632 633#define KEPLER_SET_CHANNEL_PRIORITY 0x00 634#define KEPLER_SET_CHANNEL_TIMEOUT 0x01 635 636struct kepler_set_channel_priority_v0 { 637 __u8 version; 638#define KEPLER_SET_CHANNEL_PRIORITY_LOW 0x00 639#define KEPLER_SET_CHANNEL_PRIORITY_MEDIUM 0x01 640#define KEPLER_SET_CHANNEL_PRIORITY_HIGH 0x02 641 __u8 priority; 642 __u8 pad03[6]; 643}; 644 645struct kepler_set_channel_timeout_v0 { 646 __u8 version; 647 __u8 pad03[3]; 648 __u32 timeout_ms; 649}; 650 651#endif 652